Data processing: artificial intelligence – Neural network – Learning task
Reexamination Certificate
2007-03-13
2007-03-13
Fleming, Fritz (Department: 2181)
Data processing: artificial intelligence
Neural network
Learning task
C710S001000, C710S022000, C710S033000, C710S035000, C710S052000, C710S057000
Reexamination Certificate
active
10690119
ABSTRACT:
The invention describes a modification of FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit via either an expansion bus or an external memory interface using FIFO flag initiated bursts. The hardware and FIFO signal modifications make the FIFO-DMA interface immune to deadlock conditions and generation of spurious interrupt events in the process of initiating burst transfers. The FIFO function is modified to synchronize the frame transfer on the digital signal processor even if the digital signal processor lacks this functionality. By delaying the programmable flag assertions within the FIFO until after the current burst is complete the DSP-FIFO interface may be made immune to deadlock conditions and generation of spurious events.
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Castille Kyle
Gibbs Clayton
Seshan Natarajan Kurian
Brady W. James
Fleming Fritz
Franklin Richard
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
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