FIFO for coupling asynchronous channels

Details FIFO for coupling asynchronous channels FIFO for coupling asynchronous channels

1993-03-09

1994-04-19

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 859, 370 8511, 370 91, 36518902, 36518904, 36523002, H04J 302

Patent

active

053053192

ABSTRACT:
An efficient and optimized FIFO memory for use in a bus master system utilizes a multiplexing clock from which control signal defining bus cycles on asynchronous system and local buses. The FIFO facilitates interleaved access by system and local buses to support high speed data transfers from devices on one bus to the other bus.

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patent: 4744078 (1988-05-01), Kowalczyk
patent: 4805139 (1989-02-01), Norris
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patent: 4875196 (1989-10-01), Spaderna et al.
patent: 4954987 (1990-09-01), Auvinen et al.
patent: 5001671 (1991-03-01), Koo et al.
patent: 5033045 (1991-07-01), Ramel et al.
IBM PC Advanced Troubleshooting & Repair Robert C. Brenner, Howard W. Sams & Company, 1988, "8237 Progrmmable DMA Controller (DMAC)".

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