FIFO fail-safe bus

Details FIFO fail-safe bus FIFO fail-safe bus

1995-08-22

1997-02-04

Donaghue, Larry D.

Excavating

371 681, 364184, 36494461, 3642689, G05B 902, G06F 702, H03M 1300

Patent

active

056007868

ABSTRACT:
The invention is an apparatus which utilizes relatively few conductors to provide fail-safe communication between multiple electrical subsystems and a redundant pair of data processors. This is accomplished by including two first-in, first-out memory units within each electrical subsystem, and utilizing these memory units to send the output data from the electrical subsystems on a pair of parallel data buses to a redundant pair of data processors, which then perform error tests on the data to ensure its integrity.

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patent: 5243607 (1993-09-01), Masson et al.
patent: 5317726 (1994-05-01), Horst
patent: 5349654 (1994-09-01), Bond et al.

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