FIFO control architecture and method for buffer memory access ar

Details FIFO control architecture and method for buffer memory access ar FIFO control architecture and method for buffer memory access ar

1989-03-16

1991-12-10

Fleming, Michael R.

Boots, shoes, and leggings

364939, 3649393, 36493541, 36493701, 36492794, 36492795, 364DIG2, G06F 1334, G06F 1314

Patent

active

050724207

ABSTRACT:
Access to a buffer memory is provided by a controller architecture and method employing an arbiter state machine for control of data transfer between multiple external peripheral devices and the dynamic random access memory buffer. Data transfer channels for each peripheral device include a first-in, first-out sub-buffer. Each data transfer channel communicates transfer requests to the arbiter when data is present in the FIFO. When data transfer to or from the FIFO nears an overrun or underrun condition, the data channel issues an urgent request to the arbiter state machine. The arbiter state machine prioritizes data transfer requests for enabling transfer between the buffer memory and data channels. Once a data transfer is in process it continues uninterrupted unless an urgent request is received from another device. In addition, the invention includes a refresh circuit for the dynamic RAM incorporating similar request and urgent request signals provided to the arbiter state machine for resolution.

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patent: 4272815 (1981-06-01), Kadowaki et al.
patent: 4447873 (1984-05-01), Price et al.
patent: 4760515 (1988-07-01), Malmquist et al.
patent: 4796232 (1989-01-01), House
patent: 4837677 (1989-06-01), Burrus, Jr. et al.
patent: 4847757 (1989-07-01), Smith

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