FIFO buffer system having an error detection and resetting unit

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371 211, 365 78, 36518904, H03M 1300

Patent

active

054694493

ABSTRACT:
A FIFO buffer system has an error detection and resetting unit for resetting the FIFO buffer system at the occurrence of errors therein. The system comprises M number of data storage circuits arranged in parallel for temporarily storing the N-bit input digital data and producing the N-bit output digital data in synchronization, each of said data storage circuits synchronously storing (N/M)-bit input digital data and generating storage state signals including a full flag and an empty flag signals representative of the full and the empty states thereof, respectively; and error detection and resetting unit, responsive to the storage state signals generated by said M number of data storage circuits, for generating a reset signal for resetting the FIFO buffer system when there exists a discrepancy among the full flag signal or the empty flag signals.

REFERENCES:
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patent: 4873667 (1989-10-01), Gendah et al.
patent: 5262996 (1993-11-01), Shive
patent: 5305253 (1994-04-01), Ward
patent: 5311475 (1994-05-01), Huang
patent: 5345419 (1994-09-01), Fenstermaker et al.
patent: 5349683 (1994-09-01), Wu et al.

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