Fifo buffer system having an error detection and correction devi

Details Fifo buffer system having an error detection and correction devi Fifo buffer system having an error detection and correction devi

1994-11-09

1997-01-14

Envall, Jr., Roy N.

Excavating

371 404, 395250, 36518905, G11C 2900, G11C 1134, H01J 100, H01J 506

Patent

active

055947433

ABSTRACT:
A novel FIFO buffer system has an error detection and correction device for effectively detecting and correcting errors therein. The system comprises M number of data storage blocks arranged in parallel for temporarily storing N-bit input digital data and generating storage state signals including full flag and empty flag signals representative of the full and the empty states thereof; an error detector, responsive to the storage state signals, for generating full error signals and empty error signals representative of the errors present among the full flag signals and empty flag signals; and an error corrector, responsive to the full error and the empty error signals, for generating full error correction signals and empty error correction signals for correcting the erroneous storage state occurred in the corresponding data storage means thereto.

REFERENCES:
patent: 4357702 (1982-11-01), Chase et al.
patent: 4841513 (1989-06-01), Farhangi et al.
patent: 5325487 (1994-06-01), Au et al.
patent: 5371870 (1994-12-01), Goodwin et al.
patent: 5384744 (1995-01-01), Lee

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