FIFO based receive packet throttle for receiving long strings of

Details FIFO based receive packet throttle for receiving long strings of FIFO based receive packet throttle for receiving long strings of

1995-08-10

1998-03-24

Lall, Parshotam S.

395876, G06F 0506

Patent

active

057322864

ABSTRACT:
An apparatus and method for efficiently receiving a long string of short data packets. Storing a long string of short data packets received from external devices can be inefficient in terms of system resources such as system memory and CPU time. In the preferred embodiment of the present invention, both the number of data packets in the FIFO buffer and the demand of system memory are monitored. A FIFO buffer of at least 32 bytes deep and having a packet-based threshold is implemented to monitor the number of data packets in the FIFO buffer. When the number of data packets in the FIFO buffer is equal to or exceeds the threshold and there is a predetermined number of free buffer memory available, data is transferred from the FIFO buffer to system memory. The number of data packets transferred from the FIFO buffer is also monitored to control the amount of data transfer. Any data stuck inside the FIFO buffer for a predetermined period of time is automatically unloaded. In an alternate embodiment, a FIFO buffer of at least 32 bytes deep and having an upper limit packet-based threshold and a lower limit packet-based threshold is used. A data transfer request is initiated when data in the FIFO buffer reaches the upper limit threshold. Conversely, a stop transfer request is initiated when data in the FIFO buffer is equal to or less than the lower limit threshold.

REFERENCES:
patent: 4852088 (1989-07-01), Gulick et al.
patent: 4860244 (1989-08-01), Bruckert et al.
patent: 5369775 (1994-11-01), Yamasaki et al.
patent: 5390299 (1995-02-01), Rege et al.
patent: 5434892 (1995-07-01), Dike et al.
patent: 5557750 (1996-09-01), Moore et al.

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