1992-07-07
1994-08-02
Canney, Vincent P.
Excavating
371 491, G06F 1100
Patent
active
053352351
ABSTRACT:
A flexible and implementation efficient logic circuit for a FIFO based parity generator, for generating parity blocks for use in a computer system. The logic circuit being capable of generating a data block resulting from an XOR of logic "0" with every bit in the first of a series of data blocks and storing the resulting data block in a FIFO data structure. The contents of the stored block of data may then be XORed with the contents of subsequent blocks of data with the result being stored in the FIFO data structure. The stored data, which represents the parity block generated from the series of data blocks supplied to the FIFO based parity generator, may be read out of the FIFO based parity generator over a series of clock cycles. The logic circuit of the present invention may also be used as a temporary storage media or as a logical zero generator. To use the logic circuit of the present invention as a temporary storage media, a block of data is XORed with logical "0"'s and stored in the FIFO data structure of the logic circuit the same as a first block of data. The data is then read out of the FIFO data structure before additional data is written to the FIFO data structure. To use the logic circuit of the present invention as a logical zero generator, a read operation is performed when the FIFO data structure is empty.
REFERENCES:
patent: 4538271 (1985-08-01), Kohs
patent: 5195093 (1993-03-01), Tarrab et al.
Canney Vincent P.
Digital Equipment Corporation
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