FIFO architecture with built-in intelligence for use in a graphi

Details FIFO architecture with built-in intelligence for use in a graphi FIFO architecture with built-in intelligence for use in a graphi

1998-03-13

2000-11-21

Picardat, Kevin M.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

257 66, 257 71, 257390, H01L 2184, H01L 2182

Patent

active

061506796

ABSTRACT:
The present invention provides a first-in-first-out (FIFO) memory device comprising a first latch array, a second latch array, a write pointer device, a first read pointer device, and a second read pointer device. Preferably, the FIFO memory device of the present invention is implemented in a graphics memory system having a two-bank architecture for reducing paging overhead. The second latch array is used for storing row addresses for bank0 and bank1 of the frame buffer memory of the graphics memory system. The first latch array is used for storing column addresses and any other related data for bank0 and bank1 of the frame buffer memory. When the row addresses are loaded into the second latch array, the row addresses are tagged with a bank bit that indicates which bank the row address will access. Additionally, row addresses that require re-paging of either bank0 or bank1 are tagged with a paging bit. The second read pointer device determines which of the row addresses has been tagged with a paging bit to determine which row addresses are candidates for bank0 and bank1 transactions. The second read pointer device then prioritizes the bank0 candidates and the bank1 candidates to determine which of the bank0 candidates is a dump candidate and which of the bank1 candidates is a dump candidate. The second read pointer device then prioritizes the dump candidates and selects the row address corresponding to the dump candidate that was loaded first and that will be required first. This row address is then sent to a row port output register. Once this row address has been unloaded from the row port output register, the row address corresponding to the next dump candidate can then be sent to the row port output register. This aspect of the present invention allows a row address for one bank to be loaded into the row port output register while transactions for the other bank are being processed, thus allowing re-paging to be "hidden".

REFERENCES:
patent: 5097442 (1992-03-01), Ward et al.

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