Pulse or digital communications – Synchronizers – Self-synchronizing signal
Patent
1997-09-04
2000-06-13
Nguyen, Viet Q.
Pulse or digital communications
Synchronizers
Self-synchronizing signal
375355, 375360, 375363, 375370, 375372, 375376, 370511, 379 60, 379 61, H04K 102
Patent
active
060758317
ABSTRACT:
A method for handling underflow and overflow of data in a FIFO buffer includes steps of inserting an insert data word in the FIFO buffer if there is an underflow of data at the FIFO buffer and discarding a discard data word of the FIFO buffer if there is an overflow of data at the FIFO buffer. In one embodiment, the insert data word is null and does not change the status of the FIFO buffer.
REFERENCES:
patent: 4682350 (1987-07-01), Akerberg
patent: 4803726 (1989-02-01), Levine et al.
patent: 5416779 (1995-05-01), Barnes et al.
patent: 5533027 (1996-07-01), Akerberg et al.
patent: 5666366 (1997-09-01), Malek et al.
Hendrickson Alan
Schnizlein Paul
Advanced Micro Devices
Nguyen Viet Q.
LandOfFree
FIFO and system synchronization system and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with FIFO and system synchronization system and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FIFO and system synchronization system and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2075646