Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1998-12-04
2002-09-10
Niebling, John F. (Department: 2812)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S015000
Reexamination Certificate
active
06449708
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to a field programmable processor and more particularly to such a processor capable of emulating analogue functions.
II. Related Art
In recent years there has been a widespread move in the microelectronics industry away from ‘Custom’ or ‘Semi-custom’ integrated circuits whose function is determined during manufacture towards Field Programmable components whose function is determined not when the integrated circuit is fabricated, but by an end user, ‘in the field’, prior to use.
Field Programmable Gate Arrays (FPGAs) are now widely used to implement many digital functions and offer the advantages of low non-recurring engineering costs, fast turnaround (designs can be placed and routed on an FPGA in typically a few minutes), and low risk since designs can be easily amended late on in the product design cycle. It is only for high volume production runs that there is a cost benefit in using the more traditional approaches.
However, there is no adequate equivalent to FPGAs for implementing analogue circuitry.
The concept of Field Programmable Analogue Arrays is known. Hans Klein in “The EPAC Architecture: An Expert Cell Approach to Field Programmable Analogue Arrays” (proceedings of ACM FPGA '96 Conference, February 1996) describes a device which can implement a limited set of programmable filter functions and gain stages. However, this does not offer the user any degree of design freedom in that all filters are pre-designed and the user only selects the filter which best matches his requirements.
A. Bratt and I. Macbeth describe in “Design and Implementation of a Field Programmable Analogue Array” (proceedings of ACM FPGA '96 Conference, February 1996) an array of programmable cells. Each cell contains an operational amplifier (OPAMP), multiple programmable capacitors, and switching arrangements for connecting the capacitors in such as a way as to perform the desired function. As it is difficult to manufacture accurately and reliably absolute capacitor and resistor values in typical silicon chip fabrication, a technique known as ‘switched capacitor filter design’ has been developed and is described in “Analog MOS Integrated Circuits”—R. Gregorian, G. C. Temes, published by John Wiley & Sons, Inc., 1986. In this technique, reliable filter specification is achieved by a ratio of capacitors and an accurate control of the frequency of a ‘sampling’ clock. This technique provides programming flexibility but there are still substantial disadvantages in using a device manufactured in this way.
First, owing to parasitics and imperfections in the fabrication process there is a minimum size of capacitor which can be made reliably. To provide a reasonable frequency response and programming range, the capacitors must be constructed that are many times greater than this minimum size ( say 256 time greater) and hence large areas of silicon are required thereby increasing the cost. In addition, operational amplifiers require relatively large areas of silicon in comparison to logic circuitry.
Secondly, the above measures to combat parasitics only reduce the extent of and do not eliminate the problem. For example, a practical OPAMP implementation may experience a variable +/−10 mV input differential offset between successive production runs of silicon, due to variations in transistor characteristics. Analogue circuit design is sensitive to OPAMP voltage offsets of this magnitude and in many cases it is not possible for a user to ‘design around’ this unknown quantity. In conventional analogue electronics design it is usual to provide extra pins on the OPAMP integrated circuit for the user to adjust the offset manually to zero by use of a potentiometer in those parts of the circuitry which are sensitive to these type of offsets. This is clearly not practical on an field programmable analogue array which may have 10 or 20 OPAMP elements.
Thirdly, end users require accurate simulation models to determine, with precision, behavior of the programmed circuits. The simulation models are generally complex in view of the non-ideal performance of an operational amplifier caused by well known factors such as voltage offsets, parasitic “poles”, finite gain-bandwidth product etc. Without detailed simulation tools it is possible for the same design to behave quite differently under different conditions.
Finally, the end user requires a relative high understanding of analogue design techniques to use a field programmable analogue array of this type.
It is known for digital signal processing devices to have an array of processing elements. Each processing element performs an operation on a piece of data and then passes the result forward to another element for a further operation to be carried out, possibly in combination with data output from other elements. A description of a such a processor array is given in Mead, C., Conway,
1
., “Introduction to VLSI systems”, published by Addison-Wesley, Reading, Mass., 1980 (pages 271 to 279). The connections between the processing elements of the array are fixed. These arrays are usually synchronous, i.e. input data is clocked in on one system clock pulse and the result out on the next clock pulse.
SUMMARY OF THE INVENTION
It is an object of the present invention to obviate or mitigate the aforesaid disadvantages and to provide a programmable processor capable of performing signal processing and arithmetic functions needed to emulate linear and non-linear analogue functions.
According to the present invention there is provided a field programmable processor comprising a regular array of processing elements each of which is adapted to perform a fixed function on packets of data, an array of signal conductors extending adjacent the processing elements, switching means for selectively connecting the processing elements to the adjacent signal conductors so as to interconnect the processing elements, means for storing program data representing desired processing element interconnections, means for controlling the switching means in accordance with the stored program data to achieve the desired processing element interconnections, means for storing numeric data values within each processing element, and means for synchronously transmitting packets of serial data between the interconnected processing elements.
The term “fixed function” is intended to cover at least a static arithmetic function whereby a processing element performs a dedicated arithmetic function once the processor has been defined and programmed. This does not discount the possibility of the processor being reprogrammed at a later time.
Conveniently there may be provided a further array of signal conductors extending adjacent the processing elements, the further array being arranged to convey function control data between the processing elements.
The function control data may generated by a processing element or a combination of processing elements. Preferably the function controlled by the function control data is any one of reset, set, enable or modification of the signal data.
The packets of data are conveniently synchronously transmitted between processor elements in serial form.
The fixed function of each processing element is preferably either multiply or add.
Preferably at least one processing element having the multiply function uses a shift and add operation. This enables processing of a received packet to be initiated before all the bits of that packet have arrived.
The processing elements may be arranged in an array of identical groups of elements, each group incorporating processing elements of different functions. Each identical group may comprise one processing element with the add function and three processing elements having the multiply function.
Preferably the processor element has delay means so that data on an output of the processing element is a copy of the input data delayed by the time it takes to transmit a complete packet of data.
Preferably there is provided means to transmit contr
Dewhurst Andrew
Work Gorden
Niebling John F.
Nixon & Vanderhye P.C.
Systolix Limited
Whitmore Stacy A
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