Field programmable processor devices

Details Field programmable processor devices Field programmable processor devices

1999-07-13

2001-07-17

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C326S041000

Reexamination Certificate

active

06262908

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a field programmable devices.
In particular, the invention relates to such a device comprising: a plurality of processing devices; a connection matrix interconnecting the processing devices and including a plurality of switches; a plurality of memory cells for storing data for controlling the switches to define the configuration of the interconnections of the connection matrix.
The problems with which the present invention (or at least preferred embodiments of it) is concerned are to provide more flexible use of memory, to enable higher memory density and higher circuit density.
SUMMARY OF THE INVENTION
In accordance with a first aspect of the present invention, there is provided means for isolating the effect of the data stored in at least one group of the memory cells and switches on the configuration of the interconnections so that the memory cells in that group are available for storing other data. Accordingly, the memory cells can be selectively used (a) for controlling the interconnections and (b) as user memory. By providing this feature using the configuration memory for the switches, higher memory density can be achieved.
In one embodiment, the isolating means comprises means for isolating each of the memory cells in the group from the switches. This enables isolation without requiring additional switches to be introduced into the wiring of the connection matrix, which would increase signal propagation delay and so reduce circuit speed.
This latter feature may be provided in devices which do not require memory cells to be isolated in groups. Therefore, in accordance with a second aspect of the present invention, there is provided a field programmable device, comprising: a plurality of processing devices; a connection matrix interconnecting the processing devices and including a plurality of switches; a plurality of memory cells for storing data for controlling the switches to define the configuration of the interconnections of the connection matrix; and means for isolating each of the memory cells from the switch or switches controllable by that memory cell.
The isolating means is preferably operable to set each of the switches in the group to a predetermined state upon isolation from the respective memory cell. Accordingly, when isolated, the switches may still provide a predetermined connection in the connection matrix, but they may all be set to “off”.
The isolating means preferably comprises, for each memory cell, a respective gate having inputs connected to the memory cell and to a control signal, and having an output connected to the or each switch which can be controlled by that memory cell. The use of a gate ensures that the switch is controlled by a well defined logic level at all times, whether it is being controlled by the memory cell or the control signal. Each gate may provided by four transistors, and one of the transistors of each gate may be common to a plurality of the gates, thus enabling an increased circuit density to be achieved.
In another embodiment, the isolating means comprises means for isolating each of the switches in the group from the remainder of the connection matrix.
At least some of the interconnections provided by the connection matrix may be in the form of plural-bit busses, with those of the switches for the busses each comprising a plurality of switch elements each for a respective bit of the bus.
The positions of the memory cells are preferably distributed across the device to substantially the same extent as the switches, and each of the memory cells is disposed adjacent the switch or switches controllable by that memory cell, thus enabling a high circuit density to be achieved.
This latter feature may be provided, whether or not the memory cells are isolatable. Therefore, in accordance with a third aspect of the present invention, there is provided a field programmable device, comprising: a plurality of processing devices; a connection matrix interconnecting the processing devices and including a plurality of switches; and a plurality of memory cells for storing data for controlling the switches to define the configuration of the interconnections of the connection matrix; wherein the positions of the memory cells are distributed across the device to substantially the same extent as the switches, and each of the memory cells is disposed adjacent the switch or switches controllable by that memory cell.


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