Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
1999-07-13
2001-06-26
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C326S041000
Reexamination Certificate
active
06252792
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to field programmable processor arrays, that is, arrays of processing units which are selectively connectable by signal paths one to another, and in particular to such arrays which are provided as integrated circuits.
The problems with which the present invention (or at least preferred embodiments of it) is concerned are to provide a dense circuit layout, efficient interconnections between the processing units and flexibility in the manner in which the processing units may be interconnected.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided an integrated circuit having a field programmable circuit region arranged as a generally rectangular array of rows and columns of circuit areas, wherein: some of the circuit areas each provide a respective processing unit (such as an arithmetic logic unit) for performing operations on data on at least one respective input signal path to provide data on at least one respective output signal path; others of the circuit areas each provide a respective switching section; the processing units and the switching sections are arranged alternately in each row and in each column; and each of a substantial proportion (and preferably all) of the switching sections provides a programmable connection between at least some of the signal paths of those of the processing units adjacent that switching section in the same column and in the same row. By arranging the circuit in this way, a dense layout can be obtained with efficient local interconnections, especially in the case where one or more of the processing units has a plural-bit input and/or a plural-bit output, and at least some of the signal paths are provided by respective plural-bit busses.
A first type of the connections provided by the switching sections are between such signal paths which may be generally collinear with or parallel to each other, allowing the paths to be selectably concatenated to produce longer connections. In this case and in the case where at least one of the processing units and the processing units adjacent thereto each have a first input, a second input and an output; the output of said one processing unit is preferably connectable: by such a first type of connection to the first input of the next processing unit in one direction in the same row; by such a first type of connection to the first input of the next processing unit in the one direction in the same column; by such a first type of connection to the second input of the next processing unit in the opposite direction in the same row; and by such a first type of connection to the second input of the next processing unit in the opposite direction in the same column. In this way, the output of a first processing unit can be selectably passed to any of the four adjacent processing units in the same row or column (“a second processing unit”), where it can be processed and then passed back to the first processing unit or passed on to any of the other three adjacent processing units adjacent the second processing unit.
A second type of the connections provided by the switching sections are between such signal paths which may be generally orthogonal to each other. Thus the signal paths can change direction to enable flexible routing. In this case and in the case where at least one of the processing units and the processing units adjacent thereto each have a first input, a second input and an output, the output of said one processing unit is preferably connectable: by such a second type of connection in the same column to the first input of the diagonally adjacent processing unit in said one row direction and said one column direction; by such a second type of connection in the same row to the first input of the diagonally adjacent processing unit in said opposite row direction and said one column direction; by such a second type of connection in the same column to the second input of the diagonally adjacent processing unit in said opposite row direction and said opposite column direction; and by such a second type of connection in the same row to the second input of the diagonally adjacent processing unit in said one row direction and said opposite column direction. Thus, the output from a first processing unit can be selectably routed to the first inputs of two of the diagonally adjacent processing units, and to the second inputs of the other two diagonally adjacent processing units.
Preferably substantially all of the input and output signal paths are oriented in directions substantially parallel to the rows or the columns, thus enabling a dense layout to be achieved.
The integrated circuit preferably further comprises a plurality of inter switching section signal paths, each of which extends from a respective first one of the switching sections to a respective second one of the switching sections in the same row in a direction primarily generally parallel to that row, or in the same column in a direction primarily generally parallel to that column, each of the inter switching section signal paths being programmably connectable by the respective first switching section to others of the signal paths at that first switching section, and being programmably connectable by the respective second switching section to others of the signal paths at that second switching section. Accordingly, medium and long range connections can be selectably provided.
For one type of the inter switching section signal paths, there may be no such switching sections in the respective row or column between the respective first and second switching sections.
For another type of the inter switching section signal paths, the respective first and second switching sections may have a number (preferably one less than a power of two) of other such switching sections therebetween in the respective row or column. Thus, long range connections are provided reducing the number of intermediate switches which may be required, and accordingly reducing the propagation delay which would be caused thereby.
For a further type of the inter switching section signal paths, each signal path may have a spine portion extending in a direction generally parallel to the respective row or column and first and second end portions each extending in a direction generally orthogonal to the respective row or column and interconnecting the spine portion and the respective first and second switching sections, respectively. Since the spine portions do not connect to the switches directly, the choice of the physical position of the conductors in the spine portion is flexible, and this flexibility enables denser layouts to be achieved. For at least some of the inter switching section signal paths of said further type, the respective first and second switching sections may have a number (preferably one less than a power of two) of other such switching sections therebetween in the respective row or column. Thus, long range connections are provided reducing the number of intermediate switches which may be required, and accordingly reducing the propagation delay which would be caused thereby. At least some of the inter switching section signal paths of said further type preferably each have at least one tap portion extending in a direction generally orthogonal to the respective row or column and interconnecting the spine portion and a respective such other switching section. Accordingly, even greater flexibility is provided.
At least some of the switching sections preferably each include a respective register and/or buffer having an input and an output each switchably connectable to at least some of the signal paths at that switching section. This allows signals to be retimed or buffered without using one of the processing units for that purpose. Retiming and buffering of time-critical signals allows configurations to run at higher clock speeds, increasing the rate of operation.
REFERENCES:
patent: 4236204 (1980-11-01), Groves
patent: 5204556 (1993-04-01), Shankar
patent: 5208491 (1993-05-01), Ebeling et
Marshall Alan
Stansfield Anthony
Vuillemin Jean
Elixent Limited
Nelms David
Tran M.
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