Field programmable matrix circuit for EEPROM logic cells

Details Field programmable matrix circuit for EEPROM logic cells Field programmable matrix circuit for EEPROM logic cells

1988-05-26

1989-09-12

Griffin, Robert L.

Communications: electrical

Continuously variable indicating

With meter reading

34082583, 34082585, 34082589, 307465, H04Q 300, G06F 738

Patent

active

048664324

ABSTRACT:
An improved field programmable matrix circuit. The matrix circuit includes a plurality of pairs of input lines having noninverted and inverted inputs. These input lines intersect a plurality of output column lines. A single transistor is used to provide a programmable connection to each column line from both the inverted and noninverted inputs of an input line pair. The transistor has a source, a drain and a gate with either the source or the drain coupled to a voltage potential and the other of the source or the drain coupled to an output column line. The gate is alternately coupled to a noninverted input, an inverted output, or a second voltage potential. The second voltage potential is coupled when it is desired to hold the transistor in an off state.

REFERENCES:
patent: 3720925 (1973-03-01), Ross
patent: 4495590 (1985-01-01), Mitchell, Jr.
patent: 4670749 (1987-06-01), Freeman

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