Field programmable logic array with two or planes

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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3072722, H03K 19177

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active

052202151

ABSTRACT:
A programmable logic device (PLD) is disclosed which can efficiently, in a real estate sense, emulate a Mealy state machine. Specifically, there is a PLD which has: (1) a programmable logical AND and two programmable logical OR arrays, similar to a field programmable logic array; and (2) one of the two fully programmable OR array generates a next state of the circuit and the second OR array generates an output responsive to both the inputs and the current state.

REFERENCES:
patent: 3287702 (1966-11-01), Borck, Jr. et al.
patent: 3287703 (1966-11-01), Slotnick
patent: 3296426 (1967-01-01), Ball
patent: 3313926 (1967-04-01), Minnick
patent: 3423646 (1969-01-01), Cubert et al.
patent: 3462742 (1969-08-01), Miller et al.
patent: 3473160 (1969-10-01), Wahestiom
patent: 3514543 (1970-11-01), Crawford et al.
patent: 3535498 (1970-10-01), Smith, Jr.
patent: 3566153 (1971-02-01), Spencer, Jr.
patent: 3602733 (1971-08-01), Aoki
patent: 3702985 (1972-11-01), Probsting
patent: 3737866 (1973-06-01), Gruner
patent: 3742242 (1974-02-01), Preel
patent: 3757306 (1973-09-01), Boone
patent: 3769525 (1973-10-01), Foss et al.
patent: 3774171 (1973-11-01), Regetz
patent: 3795901 (1974-03-01), Boehm et al.
patent: 3798606 (1974-03-01), Henle et al.
patent: 3803587 (1974-04-01), Mead
patent: 3816725 (1974-06-01), Greir
patent: 3818252 (1974-06-01), Chiba et al.
patent: 3818452 (1974-06-01), Greer
patent: 3832489 (1974-08-01), Krishna
patent: 3849638 (1974-11-01), Greer
patent: 3906255 (1975-09-01), Mensch, Jr.
patent: 3912947 (1975-10-01), Buchanan
patent: 3924243 (1975-12-01), Vermeulen
patent: 3967059 (1976-06-01), Moore, III et al.
patent: 3974366 (1976-08-01), Hebenstreit
patent: 3979730 (1976-09-01), Bennett et al.
patent: 3983538 (1976-09-01), Jones
patent: 3987286 (1976-10-01), Hornlager
patent: 3987410 (1976-10-01), Beausoleil et al.
patent: 3990045 (1976-11-01), Beausoleil et al.
patent: 4034349 (1977-07-01), Monaco et al.
patent: 4034356 (1977-07-01), Howley et al.
patent: 4037087 (1977-07-01), Muhldorf
patent: 4037089 (1977-07-01), Horninger
patent: 4044312 (1977-08-01), O'Ortenzio
patent: 4078259 (1978-03-01), Soulsby et al.
patent: 4091359 (1978-05-01), Rossler
patent: 4093998 (1978-06-01), Miller
patent: 4107785 (1978-08-01), Seipp
patent: 4124899 (1978-11-01), Berliner et al.
patent: 4128873 (1978-12-01), Lamlaux
patent: 4218740 (1980-08-01), Bennett et al.
patent: 4422072 (1983-12-01), Cavlan
patent: 4554640 (1985-11-01), Wong et al.
patent: 4717912 (1988-01-01), Harvey et al.
patent: 4758746 (1988-07-01), Birkner
patent: 4763020 (1988-08-01), Takata et al.
patent: 4771285 (1988-09-01), Agrawal et al.
patent: 4847612 (1989-07-01), Kaplinsky
patent: 4967107 (1990-10-01), Kaplinsky
patent: 5012135 (1991-04-01), Kaplinsky
patent: 5028821 (1991-07-01), Kaplinsky
"CMOS EPLD and Gate Arrays" ATMEL High Density UV Erasable Programmable Logic Device, pp. 19+24+20.
J. E. Elliott, et al., "Array Logic Processing", IBM Tech. Disclosure Bulletin, vol. 18, No. 21, Jul. '73, pp. 219 & 220.
H. Fleisher, et al., "Reconfigurable Machine", IBM Tech. Disclosure Bulletin, vol. 16 No. 10 Mar. 1974, pp. 221, 222 & 223.
W. Carr et al, Mos/LSI Design and Applications pp. 229-258.
H. Fleisher et al, "An Introduction to Array Logic" IBM J. Research & Development, Mar. 1975 pp. 98-104.
Jones, "Array Logic Macros" IBM J. Research and Development, Mar. 1975 pp. 120-126.
Andres, "MOS Programmable Logic Arrays" A Texas Instrument Application Report Oct. 1970 pp. 1-13.
Barna et al, Integrated Circuits in Digital Electronics John Wiley & Sons 1973, pp. 412-419 and 84-91 and FIGS. 11-34.
Wood "High Speed Dynamic Programmable Logic Array Chip" IBM J. Res. Develop. Jul. 1975, pp. 379-381.
Boysel, "Memory on a Chip: A Step Toward Large-Scale Integration" Electronics, Feb. 6, 1967 pp. 93-97.
Wilkes et al "The design of the Control Unit of an Electronic Digital Computer" The Institution of Electrical Engineers, Jun. 1957, pp. 121-128.
Mrazek, "PLAs Replace ROMs for Logic Designs" Electronic Design Oct. 25, 1973 pp. 66-70.
Howley et al. "Programmable Logic Array Decoding Technique" IBM Tech. Disclosure Bulletin, vol. 17, No. 10 Mar. 1975--p. 2988.
Hemel "The PLA: A Different Land of ROM" Electronic Design, Jan. 5, '76 pp. 78-84.
Calvan et al. "FPLA Applications--Exploring Design Problems and Solutions" pp. 63-69 source and data n/a.
Kidder, The Soul of a New Machine, 1982 pp. 118-128 and 268-269.
National Semiconductor Inc. "Data update MOS" Aug. 1972, pp. 86 and 87.
Blakeslee, Digital Design with Standard MSI and LSI, John Wiley and Sons, 1975, pp. 67-77, 94-99, and 104-105.
PAL Handbook, Monolithic Memones, Inc. 1978 p. N/A.
Hutton et al. "A Simplified Summation/Array for Cellular Logic Molecules" IEEE Trans. On Computers, Feb. 1974 pp. 203-206.
Programmable Logic--A Basic Guide for the Designer, Data I/O Corp. 1983--pp. 20-25.
The TTL Data Book for Design Engineers, Texas Instruments Inc, 1973, pp. 295-303, 473, 458 and 480.
Ramaswamy et al "Second Generation PAL Programmars" Wescon/83 Professional Program Session Record, Session 13.
Monolithic Memones Inc. Form 10-K, Oct. 3, 1982 Annual Report Pursuant to Section 13 or 15(2) of the Securities Exchange Act of 1934.
"The Role of Software in the Growth of PLDs" The Technology Research Group Letter, vol. 1, No. 13, Nov. 1985 p. 3.
Teil et al. "A Logic Memones for KLSI PLA Design" ACM IEEE Ninteenth Design Automation Conf. Proceedings, Jun. 82, pp. 156-162.
Marrin, "Programmable Logic Devices Gain Software Support" EDN Feb. 9, 1984, pp. 67-74.
Cole et al. "Next Generation Programmable Logic" Wescon/84 Professional Program Session Record, Session 19.
Monolithic Memones Annual Report 1981, Letter to Shareholders p. 2.
"Semicustom IC Update, Field Programmable Logic Devices" Visa from the Valley, Hambrecht & Just Inc. vol. 3 No. 1, Mar. 86 pp. 4-7.
Phelps, Institutional Research Report on Monolithic Memones, Inc., A publication of Woodman, Kirkpatrick & Gilbrath Aug. 30, '84.
Wood, "High-Speed Dynamic Programmable Logic Array Chip" IBM J. Res. Develop. Jul. 1975, pp. 379-381.
Cavlan et al "Field PLAS Simplify Logic Designs" reprinted from Electronic Design, Sep. 1, 1975.
Signetics Bipolar and MOS Memory, Data Manual Signetics Inc, pp. 156-165 Jan. 1979.
Dorman "PLAS on MPs at Times they Compete at Time they Cooperate" Electronic Design, 18 Sep. 1, 1976, pp. 24-30.
Elliot et al "Array Logic Processing" IBM Tech. Disclosure Bulletin, vol. 16 No. 2 Jul. 1973 pp. 586-587.
MacWorld, The Macintosh Magazine, May--Jun. 1984.
"Programmable Logic Arrays" MOS/LSI Design and Application, p. 102.
H. Fleisher et al "An Introduction to Array Logic" IBM J. Res. Development, p. 132.
"User--Programmable Logic Devices add Eraciability and Hit New Density Levels, Electronic Products, p. 276.
Use of Laser Mechanism in Printers breaks Prue and Maintenance Barriers, Jan. 15, '85 p. 277.

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