Field programmable logic array with speed optimized architecture

Details Field programmable logic array with speed optimized architecture Field programmable logic array with speed optimized architecture

1992-04-08

1993-08-10

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 3072021, H03K 19177

Patent

active

052352218

ABSTRACT:
A programmable logic device (PLD) is disclosed for finding a sum of products or other logic equations. Specifically, there is a PLD which has: 1) a programmable logical AND and programmable logical OR arrays/matrices, similar to a field programmable logic array; and 2) the fully programmable OR array has an optimized signal speed path and non-optimized signal speed path.

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