Field programmable gate array architectures and methods for...

Details Field programmable gate array architectures and methods for... Field programmable gate array architectures and methods for...

2011-01-11

2011-01-11

Trost, IV, William (Department: 2472)

Multiplex communications

Fault recovery

C370S235000, C370S538000, C714S002000

Reexamination Certificate

active

07869343

ABSTRACT:
A field-programmable gate array (“FPGA”) or programmable logic device (“PLD”) includes relatively general-purpose PLD core circuitry and relatively specialized high-speed serial interface (“HSSI”) hard IP circuitry. To better support applications that include forward error correction (“FEC”), some tasks related to FEC (e.g., FIFO operations) are performed in the PLD core circuitry, while other FEC tasks (e.g., FEC calculations) are performed in the HSSI hard IP circuitry.

REFERENCES:
patent: 4486739 (1984-12-01), Franaszek et al.
patent: 6298387 (2001-10-01), Prasad et al.
patent: 6775799 (2004-08-01), Giorgetta et al.
patent: 6778799 (2004-08-01), Shin et al.
patent: 7039067 (2006-05-01), Feinberg et al.
patent: 7372862 (2008-05-01), Wego et al.
patent: 2003/0067655 (2003-04-01), Pedersen et al.
patent: 2004/0202205 (2004-10-01), Sheth et al.
patent: 2005/0163168 (2005-07-01), Sheth et al.
patent: 2006/0256846 (2006-11-01), Oksman et al.
patent: 2007/0247936 (2007-10-01), Direnzo et al.
patent: 2008/0010582 (2008-01-01), Nieto et al.

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