Field programmable gate array

Details Field programmable gate array Field programmable gate array

1992-01-07

1993-05-04

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3074651, H03K 19173, H01L 2500

Patent

active

052084914

ABSTRACT:
A field programmable gate array (FPGA) comprising routing and logic blocks (RLBs) and segmented routing channels is disclosed. Each RLB is configurable to perform both logic functions and routing functions. A plurality of forwardly propagating RLBs (FPRLBs) and a plurality of backwardly propagating RLBs (BPRLBs) intermesh with one another to form a two-dimensional checkerboard array. Each column of the RLB array comprises a plurality of FPRLBs and BPRLBs in alternating sequence. Similarly, each row of the RLB array comprises a plurality of FPRLBs and BPRLBs in alternating sequence. The FPRLBs forwardly propagate signals and the BPRLBs backwardly propagate signals. Each FPRLB may receive a plurality of input signals from a plurality of FPRLBs in the preceding leftward column. Moreover, each FPRLB may output a plurality of output signals to a plurality of FPRLBs in the next rightward column. Similarly, each BPRLB may receive a plurality of input signals from a plurality of BPRLBs in the preceding rightward column and transmit a plurality of output signals to a plurality of BPRLBs in the next leftward column. A plurality of vertical segmented routing channels are disposed between the columns of RLBs, the vertical segmented routing channels accessible to the input and output of adjacent columns of RLBs.

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