Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2000-11-30
2003-10-07
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000, C361S009000, C361S118000
Reexamination Certificate
active
06631060
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor devices, and in particular, to a field oxide device with a zener junction for triggering breakdown of the device during an electrostatic discharge (ESD) event.
BACKGROUND OF THE INVENTION
The protection of integrated circuits against electrostatic discharge (ESD) is an important design consideration for integrated circuits. Integrated circuits are often susceptible to electrostatic discharge. For instance, substantial electrostatic charges can accumulate on a person's body during regular daily activities, such as walking on a carpet. If such a person subsequently comes in contact with a grounded integrated circuit, the charges on the person can discharge through that integrated circuit. Such a discharge produces a relatively large current which can cause damage to the integrated circuit.
In order to reduce the likelihood of damage to integrated circuits due to electrostatic discharge, ESD protection circuits or devices are designed into integrated circuits. One such device is a field oxide device (FOD). A field oxide device (FOD) is a semiconductor device consisting of n-p-n doped layers. As an ESD device, one of the n-regions is connected to an integrated circuit input/output pad and the other n-region is connected to either Vdd or VSS. During an ESD event, sufficient amount of charges build up on the integrated circuit input/output pad that causes the FOD to rapidly breakdown and conduct current with a low intrinsic resistance. The rapid conduction of the FOD causes the charges on the integrated circuit input/output pad to discharge to Vdd or Vss through the FOD. This action prevents the excessive charges to damage the integrated circuit.
FIGS. 1A-B
illustrate cross-sectional and top views of a prior art field oxide device (FOD)
100
typically used for electrostatic discharge (ESD) protection. The field oxide device (FOD)
100
typically consists of a p-doped silicon substrate
102
, an n-well
104
, a drain-side n+ diffusion region
108
(e.g. doped with arsenic), and a deeper drain-side n+ region
106
(e.g. doped with phosphorous), a source-side n+ diffusion region
116
, and a deeper source-side n+ region
114
. The field oxide device (FOD)
100
further consists of a drain-side field oxide
110
, a source-side field oxide
120
, and a field oxide
112
interposed between the drain-side n+ diffusion region
108
and the source-side n+ diffusion region
116
. In addition, the field oxide device (FOD)
100
consists of a dielectric layer
122
with openings to form a drain-side contact
126
from an overlying drain-side metal layer
130
to the drain-side n+ diffusion region
108
, and contact
124
from an overlying source-side metal layer
128
to the source-side n+ diffusion region
116
. For ESD protection applications, the drain-side metal layer
130
is typically connected to input/output pad and the source-side metal layer
128
is typically connected to either Vdd or Vss pad.
The n-well
104
is situated directly under the drain-side contact regions
108
and
106
, and serves as a barrier to prevent metal spiking into the p-doped silicon substrate
102
during an ESD event. The drain-side n+ region
106
(using for example phosphorous as a dopant) lining the bottom of the drain-side n+ diffusion region
108
improves the curvature of the junction to provide robust current densities at the junction during an ESD event. As best seen in
FIG. 1B
, the corners of the drain-side n+ regions
108
and
106
are chamfered to reduce the electric field that would exist if the corners would otherwise terminate at a point.
The prior art field oxide device (FOD)
100
has several drawbacks. The breakdown voltage of the field oxide device (FOD) is still relatively high for some applications, especially for integrated circuits having relatively thin gate oxides. Typically, it is desirable for the breakdown voltage of the field oxide device (FOD)
100
to be above the maximum allowable Vdd and below the breakdown voltage of the thinnest gate oxide of an integrated circuit. For some applications, the breakdown voltage of the thinnest gate oxide may lie below the breakdown voltage of the prior art field oxide diode (FOD)
100
, which makes the FOD useless for ESD protection. Another drawback of the prior art field oxide device (FOD)
100
is that it has a “point-like” breakdown region near the corners of the drain-side n+ diffusion region
108
. Because of the relatively small dimensions of the point-like breakdown region, the prior art field oxide device (FOD)
100
is unable to handle relatively high currents during an ESD event.
Thus, there is a need for an improved field oxide device (FOD) that is capable of achieving a lower breakdown voltage than the prior art field oxide device (FOD)
100
. There is also a need for an improved field oxide device (FOD) that has improved current handling capability over the prior art field oxide device (FOD)
100
. Such needs and others are met by the improved field oxide device (FOD) of the invention.
SUMMARY OF THE INVENTION
A new and improved field oxide device (FOD) is provided herein which is particularly useful for electrostatic discharge (ESD) protection and other applications. The field oxide device (FOD) of the invention is characterized as being capable of achieving a relatively low breakdown voltage in comparison to prior art field oxide devices (FODs). In addition, the field oxide device (FOD) of the invention has improved current handling capability during an ESD event or other situations involving relatively high currents due to having a “planar-like” breakdown region, instead of a point-like breakdown region characterized in prior art field oxide devices (FODs). Furthermore, the setting of the breakdown voltage level for the field oxide device (FOD) of the invention merely involves a relatively simple process step of controlling the doping concentration and energy for a particular doped region of the device.
The field oxide device (FOD) of the invention achieves these improvements by incorporating a zener junction to promote an earlier breakdown of the device. In particular, the field oxide device (FOD) of the invention comprises a p-doped substrate having a drain-side n+ diffusion region and a source-side n+ diffusion region which are separated by a field oxide. The field oxide device (FOD) of the invention further comprises a p+ doped region that interfaces with the drain-side diffusion region to form a zener junction. The zener junction promotes an earlier breakdown of the field oxide device (FOD) and also provides a planar-like breakdown region for higher current handling capability. The breakdown voltage of the field oxide device (FOD) of the invention can be easily set by controlling the doping concentration and energy of the p+ doped region.
The field oxide device (FOD) of the invention may further comprise one or more n+ regions at the boundary of the drain-side n+ diffusion region to provide a more gradual change of the junction from the drain-side n+ diffusion region to the p-doped substrate. In addition to the field oxide interposed between the drain-side n+ diffusion region and the source-side n+ diffusion region, field oxides can be added respectively at the drain and source ends of the device to provide isolation from other devices within an integrated circuit. Furthermore, the field oxide device (FOD) of the invention may also include an overlying metal layer that makes electrical contact with the drain-side n+ diffusion region and another metal layer that makes electrical contact to the source-side n+ diffusion region. A dielectric layer may separate the drain and source metal layers from the top surface of the substrate. For ESD protection applications, the drain metal layer is typically connected to input/output pad, and the source metal layer is typically connected to Vdd or Vss pad.
Other aspects, features, and techn
Chan Kaiman
Liu Chun-Mai
Su Kung-Yen
Jackson Stephen W.
Winbond Electronics Corporation
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