Static information storage and retrieval – Addressing
Patent
1996-06-06
1999-12-21
Swann, Tod R.
Static information storage and retrieval
Addressing
365 78, 36518904, 36518912, 36523003, 711109, 711169, G11C 1300
Patent
active
06005820&
DESCRIPTION:
BRIEF SUMMARY
This invention relates to field memories (FMEM) including those using, for example, dynamic random access memory (DRAM) technology.
A dynamic memory cell is one which stores data as charge, or absence of charge, on a capacitor. Typically the cell isolates the capacitor from the data (bit) line with a transistor switch such that when no read or write operation is required there is essentially no power demand to maintain the data. However, normal leakage normally requires that the charge be periodically restored. This periodic restoration of the charge is known as the refresh process.
A Field Memory (FMEM) is sequential-access memory, of the First-In First-out (FIFO) type. Currently, the central memory of a FMEM has a typical capacity of one to four mega-bit (1-4 Mb) and, to achieve high integration of densities, consists, for example, of an array of dynamic cells derived directly from DRAM technology.
FMEM's are devices in which the read and write operations may be asynchronous. Two distinct uncorrelated clocks may be used. Alteratively, the read and write operations may be synchronised using a single clock.
A very important feature of all FMEM is their high operating speed with clock frequencies between 30 MHz and 50 MHz, for example.
The technology employed has a determining influence on the general architecture of FMEM, in particular on the physical arrangement of the registers within the device. The present invention provides an improved field memory having an improved architecture. Such an improved architecture results in a more efficient structure and layout on integrated circuit which forms the device.
The present invention also provides an improved implementation of the input enable function.
The present invention yet further provides a cache arrangement for improved access.
According to the present invention in one aspect thereof, there is provided a field memory arranged in blocks to store data and wherein each block stores a bit or bits of said word, said bits having a predetermined position within said word.
A field memory in accordance with the present invention may be described as a distributed architecture, as the bits of the word are "distributed" among the blocks of the array. Distributed architecture is more efficient than conventional technology in solving the problem of transferring data between the input/output (I/O) buffers and the internal registers of the buffer.
In one embodiment of the present invention, the field memory is divided into blocks having registers, with each bit uniquely associated with one register bank.
In order that features and advantages of the present invention may be more fully appreciated, embodiments will now be described by way of example only and with reference to the accompanying drawings of which:
FIG. 1 is an architectural diagram of a field memory device,
FIG. 2 is a diagram to show the arrangement of one block of central memory.
FIG. 3 is an architectural showing distributed architecture,
FIG. 4 is an architectural diagram showing a further example of an embodiment employing distributed architecture,
FIG. 5A is a transfer gate arrangement,
FIG. 5B is a timing diagram,
FIG. 6 shows an FMEM with a cache memory,
FIG. 7 shows a cache memory with timing diagrams, and
FIG. 8 shows a memory access arrangement.
By way of example, the embodiments described refer to field memories employing in its original form conventional technology, such as 4 Mb DRAM technology. The concept of distributed architecture, would however, benefit other applications and technology. For example, both current and future 16 Mb DRAM technology. This embodiment illustrates the distributed architectural solution as applied to the problem of transferring data between the I/O buffers and the registers. The architecture described solves the transfer problem more efficiently than prior technology.
The Field Memory, shown as a block diagram in FIG. 1, has a central memory which is sub-divided into 8 blocks, numbered 1 to 8 (FIG. 1). Each block, as shown in FIG. 2, contains three mini-arrays (2
REFERENCES:
patent: 3623020 (1971-11-01), Mao
patent: 3898632 (1975-08-01), Spencer
patent: 3967251 (1976-06-01), Levine
patent: 4914630 (1990-04-01), Fujishima et al.
patent: 5027318 (1991-06-01), Wischermann
patent: 5200925 (1993-04-01), Morooka
patent: 5371714 (1994-12-01), Matsuda et al.
patent: 5394366 (1995-02-01), Miyamoto
patent: 5469400 (1995-11-01), Yamano
patent: 5537346 (1996-07-01), Seo et al.
patent: 5621679 (1997-04-01), Seo et al.
Patent Abstracts of Japan, vol. 6 No. 13 (p.-99) [891], Jan. 26, 1982 & JP-A-56 137581 (Toshiba), Oct. 27, 1981, see abstract.
Imondi Giuliano
Menichelli Stefano
Sansone Carlo
Donaldson Richard L.
Petersen Bret J.
Swann Tod R.
Texas Instruments Incorporated
Tzeng Fred F.
LandOfFree
Field memories does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Field memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Field memories will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-511857