Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-08-12
2001-01-16
Hjerpe, Richard A. (Department: 2774)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
Reexamination Certificate
active
06175344
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field emission image display utilizing field emission and to a method of driving the same.
2. Description of the Related Art
When the electric field at a surface of a metal or semiconductor is as large as 10
9
V/m, electrons pass through the potential barrier because of the tunnel effect, thus emitting out in a vacuum at room temperatures. This phenomenon is called field emission. The cathode which emits electrons on the principle is referred to as a field emission cathode.
Recently, flat emission type field emission cathodes each formed of an array of micron-size field emission type cathodes have been able to be manufactured fully using semiconductor processing technology.
The structure of a field emission cathode called a Spindt type cathode is schematically shown in FIGS.
13
(
a
) and
13
(
b
).
FIG.
13
(
a
) is a perspective view showing a FEC fabricated using the semiconductor fine-patterning technology. FIG.
13
(
b
) is a cross-sectional view illustrating the FEC taken along the line A—A shown in FIG.
13
(
a
).
Referring to FIGS.
13
(
a
) and
13
(
b
), cathode electrodes
102
of aluminum are formed on a cathode substrate
101
of glass by using vapor deposition. Cone emitters
105
are formed on the cathode electrode
102
. A great number of gate electrodes
104
are formed over the cathode electrode
102
where the cone emitter
105
are not formed, via the insulating layer
103
of silicon dioxide (SiO
2
). The cone emitters
105
are respectively positioned in the openings formed in the gate electrode
104
and the insulating layer
103
. That is, the tip of each cone emitter
105
is viewed in the opening formed in the gate electrode
104
.
The pitch between the cone emitters
105
are fabricated to be less than 10 microns, using fine-patterning technology. Thus, several tens of thousands of FECs
105
to several hundreds of thousands of FECs
105
can be fabricated on a single substrate
101
. The distance between the gate electrode
104
and the tip of the emitter
105
can be set in the order of submicrons. Hence the emitter
105
can emit electrons caused by the field emission by applying a small voltage of several ten volts between the gate electrode
104
and the cathode electrode
102
.
The FEC can be made as a flat field emission cathode by forming an array of a great number of emitters
105
as shown in FIGS.
13
(
a
) and
13
(
b
). It has been proposed to apply the flat field emission cathode to flat color display panels. The cross-section of the color image display panel is partially shown in FIG.
14
.
In
FIG. 14
, plural stripe cathode electrodes
102
are formed on the first substrate (cathode substrate)
101
of glass. Plural stripe gate electrodes
104
are arranged perpendicularly to the stripe-like cathode electrodes
102
. The insulating layer
103
separates the cathode electrodes
102
from the gate electrodes
104
. A great number of openings are respectively formed at the intersections where the cathode electrodes
102
and the gate electrodes
104
cross. The tip of each cone emitter
105
formed on the cathode electrode
102
within each opening directs upward.
The second substrate (anode substrate)
110
of glass is disposed so as to confront the first substrate
101
. Metal anode electrodes
111
are formed nearly on the entire surface of the second substrate
110
. Red fluorescent substance stripes
112
(R), green fluorescent substance stripes
113
(G), and blue fluorescent substance stripes
112
(B) are coated in one-to-one relationship at the corresponding positions of cathode electrodes
102
overlaying each anode electrode
111
.
In the color image display with the above-mentioned structure, the stripe gate electrodes
104
are sequentially scanned one by one, and red, green and blue image data corresponding to one line selected with the gate electrode
104
are supplied to the stripe cathode electrodes
102
. Thus, electrons of the amount corresponding to said image data are field-emitted from the emitter
105
disposed at the intersection of the gate electrode
104
and the cathode electrode
102
associated with the line in a driven state. The electrons impinge and glow the corresponding fluorescent substances
112
to
114
. In such a manner, when all gates
104
are sequentially scanned and selectively driven, a full color image for one frame is displayed.
Generally, in the field emission image display, electrons emitted from the cone emitter
105
reach the anode electrode
111
with a beam angle of about 30. This means that electrons reach the anode electrode
111
with some divergence. This may cause electrons emitted from the emitter
105
to glow a adjacent different color fluorescent substances disposed on the anode substrate
111
. Hence, there is the problem of blurring the displayed color image.
In order to solve such a problem, the present applicant proposed a field emission image display that can display blur-free color images by focusing electrons emitted from the emitter
105
(refer to Japanese Laid-open Patent publication (Tokkai-Hei) No. 8-298075).
FIG. 15
is a top view illustrating the field emission image display previously proposed.
Referring to
FIG. 15
, plural cathode electrodes
102
(depicted in chain lines) arranged on the first substrate are connected to cathode lead-out electrodes C
1
, C
2
, . . . , respectively.
Patchlike gate electrodes
120
corresponding to dots are arranged in two-dimensional matrix form on the cathode substrate
102
via an insulating layer (not shown). Two patchlike gate electrodes
120
are disposed on each cathode electrode
102
in the line direction perpendicular line direction. The emitters
105
(not shown) are arranged in an array pattern at the positions corresponding to the patchlike gate electrodes
120
on the cathode substrate
102
.
The anode electrode
111
(shown in broken lines) is formed on the nearly entire surface of the second substrate (anode substrate) disposed corresponding to the cathode electrodes
102
. R, G and B fluorescent substances are coated at the positions corresponding to the patchlike gate electrodes
120
on the anode electrode
111
. In
FIG. 15
, symbols R, G and B labeled on each patchlike gate electrode
120
represent the luminous color of a fluorescent substance dot coated on the anode electrode
111
.
As shown in
FIG. 15
, gate lead-out electrodes G are respectively connected to the patchlike gate electrodes arranged in the two-dimensional matrix. That is, the patchlike gate electrodes
120
corresponding to the odd-numbered G, B and R dots associated with the (i)-th line (column) are connected to the gate lead-out electrode GT
(i)−1
. The patchlike gate electrodes
120
corresponding to the even-numbered R, G, and B dots associated with the (i)-th line are connected to the gate lead-out electrode GT
(i)−2
.
The patchlike gate electrodes
120
corresponding to the odd-numbered G, B and R dots associated with the (i+1)-th line are connected to the gate lead-out electrode GT
(i+1)−1
. The patchlike gate electrodes
120
corresponding to the even-numbered R, G and B dots associated with the (i+1)-th line are connected to the gate lead-out electrode GT
(i+1)−2
. That is, two gate lead-out electrodes GT are alternately connected to patchlike gate electrodes
120
associated with each line.
A gate drive voltage is sequentially applied to the gate lead-out electrodes GT
(1)
to GT
(n)
. When the gate lead-out electrode GT
(i)−2
, for example, is driven, the even-numbered R, G and B dots (hatched) associated with the (i)-th line are driven. An image can be displayed when the cathode lead-out electrodes
102
,
102
, . . . corresponding to the patchlike gate electrodes
120
supply the corresponding image data in agreement with the scanning timing of the gate electrodes. In such a condition, by setting the gate lead-out electrodes GT
(i)−1
, GT
(i+1)−1
, GT
(i+1)−2
Futaba Denshi Kogyo Kabushiki Kaisha
Hjerpe Richard A.
Laneau Ronald
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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