Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
2000-02-10
2001-12-11
Philogene, Haissa (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C315S169100, C345S074100, C345S076000, C345S077000
Reexamination Certificate
active
06329759
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field emission image display. Particularly, the present invention relates to a display device suitable to field emission color displays.
2. Description of the Prior Art
When the electric field applied to the surface of a metal or semiconductor becomes about 10
9
volts/m, electrons pierce the barrier based on the tunnel effect and are emitted into a vacuum even at room temperatures. This phenomenon is called field emission. The cathode that emits electrons based on the principle is called a field emission cathode.
Recently, area field emission elements, each of which is formed of an array of micron-size field emission elements (hereinafter merely referred to as FEC), have been able to be produced by fully using the semiconductor fabrication technique. Field emission displays (hereinafter referred to as FEDs), each which uses FECs as an electron emission source, are being developed.
FIG. 7
is an explanatory diagram schematically illustrating a flat color FED using area field emission cathodes.
Referring to
FIG. 7
, aluminum stripe-like cathode electrodes
102
are vapor deposited on a glass cathode substrate
101
. A large number of cone emitters
105
are formed on the cathode electrodes. An insulating layer
103
of silicon dioxide (SiO2) is formed on the area where emitters
105
are not formed. Gate electrodes
104
are formed on the insulating layer
103
. Openings are formed in the insulating layer
103
and the gate electrodes
104
. Cone emitters
105
are arranged in the openings. That is, the tip of each emitter
105
is viewed from the opening of the gate electrode
104
.
The glass anode substrate
110
is disposed so as to confront the cathode substrate
101
. Anode electrodes
111
of an ITO (indium-tin-oxide) thin film are formed on the anode substrate
110
.
A red (R) fluorescent substance
112
, a green (G) fluorescent substance
112
, and a blue (B) fluorescent substance
112
are coated on the anode electrodes
111
so as to confront the openings in the gate electrodes
104
.
In the color FED with the above configuration, if each gate electrode
104
is shaped in a stripe pattern, the gate electrodes
104
are sequentially scanned and driven line by line. R image data, G image data, and B image data corresponding to a selected line of gate electrodes
104
are supplied to the stripe cathode electrodes
102
.
The emitter
105
, disposed at an intersection of the cathode electrode
102
and a line of gate electrodes
104
in a driven state, field emits an amount of electrons corresponding to the image data. The emitted electrons impinge the fluorescent substances
112
to
114
arranged at the confronting position to light-emit the corresponding fluorescent substances.
Thus, the gate electrodes are sequentially scanned. When all the gate electrodes
104
are selectively driven, a full color image for one frame is displayed on the anode substrate
110
.
In the color FED, the electrons emitted from each cone emitter
105
reach the anode electrode
111
with a divergent angle of about 30. This means that electrons reaching the anode electrode
111
diverge to a certain degree. For that reason, electrons emitted from the emitter
105
light-emit different color fluorescent substances adjacently arranged on the anode electrode
111
. This causes the displayed color image to be blurred in color.
In order to solve such a problem, the present applicant proposed the field emission image display that can display a blurless color image by converging electrons emitted from the emitter
105
(refer to Japanese Patent Laid-Open Publication No. Hei 8-298075).
FIG. 8
is a diagram illustrating an arrangement of anode electrodes and cathode electrodes of a FED proposed by the present applicant.
Referring to
FIG. 8
, the gate electrode
104
is shaped in a patch-like pattern corresponding to one dot. Gate electrodes
104
are arranged in a two-dimensional matrix on the cathode electrode not shown in FIG.
8
.
Each of the anode electrodes
111
(shown in chain lines) is a stripe-like anode electrode formed on the anode substrate
110
. R, G, and B fluorescent substances are coated on the anode substrate
111
so as to confront the patch-like gate electrodes
104
respectively. In
FIG. 8
, symbol R, B, or B with each patch-like gate electrode
104
represents the luminous color of a fluorescent substance dot coated on the anode substrate
111
.
The stripe-like anode electrodes
111
are connected to anode lead line A
1
or A
2
every other column.
Two gate lead electrodes are disposed to patch-like gate electrodes
104
of each line, as shown in FIG.
8
. For instance, the patch-like gate electrodes
104
corresponding to odd-numbered R, B, and G dots among the patch-like gate electrodes
104
of the first line (row) are connected to the gate lead electrode G
1
. The patch-like gate electrodes
104
corresponding to the even-numbered R, B, and G dots of the first line are connected to the gate lead electrode G
2
.
The patch-like gate electrodes
104
corresponding to odd-numbered G, B, and R dots among the patch-like gate electrodes
104
of the second line are connected to the gate lead electrode G
3
. The patch-like gate electrodes
104
corresponding to the even-numbered R, G, and B dots of the second line are connected to the gate lead electrode G
4
.
A gate drive voltage is sequentially applied to the gate lead electrodes G
1
, G
2
, . . . . For instance, when the gate lead electrode G
2
is driven, the even-numbered G, B, and R dots (hatched) of the first line glow.
The image data corresponding to the scanned patch-like gate electrodes
104
is supplied to the cathode electrode in synchronism with the scanning timing of the gate lead electrodes G
1
, G
2
, . . . to display an image.
At this time, the potentials of the gate lead electrodes G
1
, G
3
, G
4
, . . . not driven are set to a level lower than the potential of the driven gate leading electrode G
2
, preferably to the ground level. Thus, the gate electrodes
104
adjacent to the driven patch-like gate electrode
104
(hatched) are set to a low level. This condition allows electrons emitted from the patch-like gate electrode
104
to be converged to the anode electrode so that the color blurring can be eliminated.
FIG. 9
is a block diagram illustrating the configuration of a drive circuit embodying the method of driving the FED shown in FIG.
8
.
FIG. 10
is a diagram illustrating the operational timing of the drive circuit.
In
FIG. 9
, numeral
50
represents a field emission display formed of a matrix of (m×n) pixels. Numeral
51
represents a clock generator that generates clocks synchronized with synchronous signals. Numeral
52
represents a display timing control circuit that controls the display timing with clocks from the clock generators
51
. Numeral
53
represents a memory write control circuit that controls to write image data to a video memory
54
. Numeral
54
represents a frame memory that stores R image data, G image data, and B image data or a video memory formed of line memories
54
-
1
,
54
-
2
, and
54
-
3
. Each of numerals
55
-
1
,
55
-
2
and
55
-
3
represents a buffer register that stores R image data, G image data, and B image data read out of the video memory
54
.
Numeral
56
represents an address counter that generates addresses of the video memory
54
. Numeral
57
represents a color selection circuit that selects any one of R image data, G image data, and B image data. Numeral
58
represents a shift register that shifts data controlling the gate electrodes
3
. Numeral
59
represents a latch circuit that latches data of the shift register
58
. Numeral
60
represents a gate driver that drives gate electrodes
59
of the FED
50
according to data from the latch circuit
59
. Numeral
61
represents a shift register that shifts image data supplied from the buffer registers
55
-
1
to
55
-
3
with shift clocks. Numeral
62
represents a latch circuit that data of the shift
Takayama Katsumi
Tanaka Mitsuru
Futaba Denshi Kogyo Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Philogene Haissa
Vo Tuyet T.
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