Electric lamp and discharge devices – Cathode ray tube – Beam deflecting means
Reexamination Certificate
2000-06-30
2001-07-03
Ramsey, Kenneth J. (Department: 2879)
Electric lamp and discharge devices
Cathode ray tube
Beam deflecting means
C445S024000, C228S180220, C438S613000
Reexamination Certificate
active
06255769
ABSTRACT:
TECHNICAL FIELD
The present invention relates to field emission displays, and, more particularly, to field emission displays with raised conductive features formed at selected bonding locations between the baseplates and the faceplates of the field emission displays.
BACKGROUND OF THE INVENTION
Field emission displays (“FEDs”) are flat panel displays for use in computers, television sets, instrument displays, camcorder view finders and a variety of other applications. FEDs generally have a faceplate with a glass panel, a substantially transparent anode covering an inner surface of the glass panel, and a cathodoluminescent film covering the anode. FEDs also have a baseplate with an emitter substrate and an extraction grid. As described below, the faceplate and baseplate are generally spaced apart from one another so that the cathodoluminescent film is juxtaposed to the emitter substrate and the extraction grid.
FIG. 1
illustrates a portion of a conventional FED baseplate
20
with an emitter substrate
30
that carries a plurality of emitters
32
. The emitter substrate
30
also carries a dielectric layer
40
with a plurality of cavities
42
around the emitters
32
, and the dielectric layer
40
supports a conductive extraction grid
50
with a plurality of holes
52
over the emitters
32
. The cavities
42
and the holes
52
expose the emitters
32
to the cathodoluminescent film on the faceplate (not shown).
FIG. 2
is a top schematic view of the baseplate
20
that illustrates one technique for extracting electrons from selected emitters. The emitters
32
may be grouped into discrete emitter sets
33
configured in rows (e.g., R
1
-R
3
) and columns (e.g, C
1
-C
2
). A number of high-speed row interconnects
55
on the extraction grid
50
commonly connect a plurality of emitter sets
33
along row address lines, and a number of high-speed column interconnects
37
on the emitter substrate
30
commonly connect emitter sets
33
along column address lines. As best shown in
FIG. 1
, the row interconnects
55
are formed on top of the extraction grid
50
and the column interconnects
37
are formed beneath the extraction grid
50
. It will be appreciated that the row and column assignments illustrated in
FIGS. 1 and 2
are for illustrative purposes only, and that other row/column assignments may be implemented in field emission displays.
To operate a specific emitter set
33
, drive circuitry (not shown) generates row and columns signals along the coordinates of the specific emitter set
33
to create a voltage differential between the extraction grid and the specific emitter set. Referring to
FIG. 2
, for example, a row signal along row R
2
of the extraction grid
50
and a column signal along column C
1
of the emitter substrate
30
activates the emitter set
33
at the intersection of row R
2
and column C
1
. The voltage differential between the extraction grid
50
and the selected emitter set
33
produces a localized electric field that extracts electrons from the emitters
32
in the selected emitter set. The anode on the faceplate then attracts the extracted electrons across a vacuum gap between the extraction grid and the cathodoluminescent layer. As the electrons strike the cathodoluminescent layer, light emits from the impact site and travels through the anode and the display screen. The emitted light from each area becomes all or part of a picture element.
Constructing FEDs raises several manufacturing issues that are best understood in light of the relationship between the baseplate and the faceplate.
FIG. 3
is an exploded schematic cross-sectional view of a conventional FED
10
with the baseplate
20
and a faceplate
60
. In addition to the components described above in
FIGS. 1 and 2
, the baseplate
20
also has a plurality of bond pads
36
in or on the emitter substrate
30
such that each bond pad
36
is coupled to an end of a column interconnect
37
to provide contact points for the drive circuitry of a particular column of emitter sets
33
. The faceplate
60
has a transparent substrate
62
, an optically transmissive anode
64
covering the transparent substrate
62
, and a cathodoluminescent film
66
covering the anode
64
. The faceplate
60
also has spacers
63
a
and
63
b
on opposite sides of the anode
64
and the cathodoluminescent film
66
. A number of leads
80
(only one shown on each side) coupled to the drive circuitry (not shown) extend to the spacers
63
a
and
63
b
, and each lead
80
has a connector pad
82
and a raised feature
84
positioned on one of the spacers
63
a
or
63
b
. The raised features
84
are formed in a pattern corresponding to the pattern of bond pads
36
in the baseplate
20
. The leads
80
and connector pads
82
are typically aluminum traces having a thickness of 12-20 &mgr;m, and the raised features
84
are typically 20-50 &mgr;m points formed by individually pinching the aluminum of the connector pads
82
.
One particular manufacturing concern is that attaching the baseplate
20
to the faceplate
60
is a time-consuming and labor intensive process. For example, because the raised features
84
are formed individually by pinching the connector pads
82
, it takes a significant amount of time to form all of the raised features
84
. Moreover, because the bond pads
36
are typically quite small and spaced very close to one another, some of the raised features
84
may not align with a corresponding bond pad
36
when the baseplate
20
and the faceplate
60
are juxtaposed to one another. Such misalignment between the bond pads
36
and the raised features
84
may accordingly damage the baseplate
20
or severely impair the performance of the FED when the faceplate
60
is attached to the baseplate
20
. Many FEDs
10
, therefore, must be tested individually and either repaired or thrown-away. Thus, forming the raised features
84
is a problematic aspect of constructing FEDs.
SUMMARY OF THE INVENTION
The present invention is directed toward FEDs with raised features for connecting leads on a faceplate to terminals on a baseplate, and methods for forming the raised features. Some embodiments are particularly useful for forming raised features used in flip-chip bonding processes in which a plurality of bonding locations on the faceplate and the baseplate are coupled together. In accordance with an embodiment of the invention, a plurality of applicators are configured to correspond to a pattern of bonding locations on the baseplate or the faceplate. The bonding locations and applicators are aligned with each other such that each bonding location is positioned with respect to a corresponding applicator. A predetermined quantity of a thick film conductive bonding material is then deposited substantially simultaneously through each applicator to form a small pad of conductive material at each bonding location. The pads of thick film conductive bonding material are subsequently fired to form a raised feature at each bonding location.
In another embodiment for forming conductive raised features on a plate of a field emission display, a plurality of connector pads are formed at bonding locations on the plate. The connector pads may be traces composed of gold, copper or other suitably conductive and malleable materials. A die with a plurality of recesses configured in a pattern corresponding to the pattern of bonding locations is then positioned over the plate to align the recesses with the corresponding bonding locations. After the die is positioned over the plate, the die presses against the connector pads to drive a portion of each connector pad into a corresponding recess. The portions of the connector pads in the recesses forms a plurality of raised features on the plate such that a raised feature extends upwardly from each connector pad at a desired bonding location.
REFERENCES:
patent: 4376505 (1983-03-01), Wojcik
patent: 4940916 (1990-07-01), Borel et al.
patent: 5116228 (1992-05-01), Kabeshita et al.
patent: 5186670 (1993-02-01), Doan et al.
patent: 5194344 (1993-03-01), Cathey,
Cathey David A.
Watkins Charles M.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Ramsey Kenneth J.
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