Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Patent
1995-11-07
2000-09-12
Brier, Jeffery
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
313495, G09G 306
Patent
active
061184179
ABSTRACT:
The present invention enables a reduction in the number of electrical conductors which must be connected to each pixel in a field emission display. A first feature of the invention is that the functions of a conventional power supply ground conductor and a conventional "row enable" logic signal conductor are combined in a single "inverted row enable" logic signal conductor for each display row. A second feature is that the functions of a conventional "column enable" logic signal conductor and a conventional luminance signal conductor are combined in a "column luminance" signal conductor for each display column. The first feature is implemented by connecting the "inverted row enable" logic signal conductor as the source of emitter tip current for all the pixels in a display row. The second feature is implemented by gating (logically ANDing) a luminance signal by a "column enable" logic function to create a column luminance signal for each display column. The current flow through the emitter tips of each pixel, and hence the luminance of each pixel, is controlled by a transistor connected in series between the emitter tips of that pixel and the "row enable" signal conductor for the display row containing that pixel. The gate of the transistor connects to a conductor carrying the "column luminance" signal for the display column containing that pixel.
REFERENCES:
patent: 4229766 (1980-10-01), Sipos
patent: 4743096 (1988-05-01), Wakai et al.
patent: 4857799 (1989-08-01), Spindt
patent: 4866349 (1989-09-01), Weber et al.
patent: 4908539 (1990-03-01), Meyer
patent: 4924215 (1990-05-01), Nelson
patent: 5036317 (1991-07-01), Buzak
patent: 5075596 (1991-12-01), Young et al.
patent: 5103144 (1992-04-01), Dunham
patent: 5153483 (1992-10-01), Kishino et al.
patent: 5157309 (1992-10-01), Parker
patent: 5210472 (1993-05-01), Casper et al.
patent: 5262698 (1993-11-01), Dunham
patent: 5313140 (1994-05-01), Smith
patent: 5357172 (1994-10-01), Lee et al.
patent: 5359256 (1994-10-01), Gray
patent: 5387844 (1995-02-01), Browning
patent: 5402041 (1995-03-01), Kishino et al.
patent: 5404081 (1995-04-01), Kane et al.
patent: 5410218 (1995-04-01), Hush
patent: 5475396 (1995-12-01), Kitajima
patent: 5555000 (1996-09-01), Sarrasim et al.
patent: 5581159 (1996-12-01), Lee et al.
patent: 5598156 (1997-01-01), Hush et al.
patent: 5616991 (1997-04-01), Casper et al.
patent: 5631664 (1997-05-01), Adachi et al.
patent: 5638085 (1997-06-01), Hush et al.
patent: 5638086 (1997-06-01), Lee et al.
patent: 5642017 (1997-06-01), Hush
patent: 5783910 (1998-07-01), Casper et al.
Brier Jeffery
Micro)n Technology, Inc.
Stern Robert J.
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