Field emission display device

Details Field emission display device Field emission display device

1999-11-18

2001-03-20

Wong, Don (Department: 2821)

Electric lamp and discharge devices: systems

Plural power supplies

Plural cathode and/or anode load device

C315S169400, C345S076000

Reexamination Certificate

active

06204608

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field emission display device, and more particularly relates to a field emission display device that is able to achieve a high-luminance display panel with high aperture ratio and large-size fabricating capability.
2. Information Disclosure Statement
A field emission display device generally represents a device in which a field emission device is applied to a flat panel display device. This kind of field emission display device is produced by vacuum packaging a lower plate having a field emitter array and an upper plate having a phosphor, in parallel with narrow gap (within 2 mm), and it displays an image by the cathode luminescence of the phosphor caused by bombarding electrons that are emitted from the field emitters of the lower plate into the phosphor of the upper plate. Recently, it is widely researched and developed as a substitutional flat panel display for the conventional cathode ray tube (CRT).
A field emission display device is classified into a simple matrix type panel and an active matrix type panel according to the structure of the pixels arranged in matrix on the lower plate. In case of a simple matrix type panel each pixel comprises only a field emitter arrays, whereas of an active matrix type panel each pixel comprises a field emitter arrays and semiconductor devices (mainly, transistors) that controls field emission currents of the field emitter array. A prior active matrix type panel is illustrated in FIG.
1
and FIG.
2
.
FIG. 1
is an overall schematic diagram illustrating a lower plate structure of a prior field emission display device. Each pixel formed on a single crystal silicon wafer
10
P comprises a field emitter array
20
P comprising a plurality of triode-type field emitters, a control transistor
30
P having a drain connected to the emitter electrode of the field emitter array
20
P, a memory capacitor
40
P having an upper electrode connected to the gate electrode of the control transistor
30
P, and an addressing transistor
50
P having a drain connected to the upper electrode of the memory capacitor
40
P. The addressing transistor
50
P writes scan signals and data signals from a signal line of a display into each pixel, the memory capacitor
40
P stores the data signals of a display, and the control transistor
30
P controls field emission currents of the field emitter array
20
P according to the data signals.
A detailed structure of the pixel is illustrated in FIG.
2
.
In a prior active matrix field emission display device, a pixel, which compose a lower plate, comprises; a p-type silicon wafer
10
P, an addressing transistor
50
P comprising a source
501
P/drain
502
P, made of n-type silicon, formed on said wafer
10
P, a gate
504
P formed on the upper part of the wafer
10
P, a source electrode
505
P formed on the upper part of the wafer
10
P and electrically connected to the source
501
P, and a gate insulation film
503
P to electrically insulate the gate
504
P from the source
501
P/drain
502
P and silicon channel
10
P, a memory capacitor
40
P comprising a lower electrode
401
P, formed on the wafer
10
P, made of n-type silicon, an upper electrode
403
P, formed on the upper part of the wafer
10
P, make of metal or n-type silicon, and a gate dielectric film
402
P between the lower electrode
401
P and the upper electrode
403
P, a control transistor
30
P comprising a source
301
P/drain
302
P, formed on the wafer
10
P, made of n-type silicon, a gate
304
P formed on the upper part of the wafer
10
P, a source electrode
305
P formed on the upper part of the wafer
10
P and electrically connected to the source
301
P, and a gate insulation film
303
P to electrically insulate the gate
304
P from the source
301
P/drain
302
P and silicon channel
10
P, a field emitter array
20
P comprising a plurality of field emitter tips
201
P formed on the drain
302
P of the control transistor
30
P and a gate
202
P, and a connection electrode
345
P connected to drain
502
P of the addressing transistor
50
P, an upper electrode
403
P of the memory capacitor
40
P, and a gate electrode
304
P of the control transistor
30
P.
The display device is operated by applying a prescribed voltage required for a field emission to the gate
202
P of the field emitter array
20
P, thereafter writing a scan and a data signal of a display to the gate
504
P and the source
501
P of the addressing transistor
50
P. Once the signal is written, it is stored in the memory capacitor
40
P and continuously operates the control transistor
30
P until the next scan signal arrives (In other words, the control transistor
30
P is being operated continuously even in non-scan interval.). Therefore, it is accomplished to largely increase the average emission current of a given field emitter array, thereby largely increase the brightness of a display.
The lower plate of a prior field emission display device, by the benefit of using a single crystal silicon wafer
10
P, can produce a high-performance addressing transistor
50
P, memory capacitor
40
P and control transistor
30
P, thereby easily produce a high performance active matrix field emission display device. However, it can not produce a large size display device because of the high price of a single crystal silicon wafer
10
P and the limit of the size thereof. And the vacuum packaging is difficult because of the mechanical weakness of a single crystal silicon wafer
10
P.
In addition, the lower plate of a prior field emission display device has a good data signal holding performance because it has an independent memory capacitor
40
P in each pixel, however, it has the demerits that is needs additional processes for the fabrication of the memory capacitor
40
P and an aperture ratio of a pixel is decreased because of the area reduction by the memory capacitor
40
P existence.
SUMMARY OF THE INVENTION
It is therefore the object of the present invention to provide a field emission display device, which is able to provide an active matrix display having a memory function and to eliminate a conventional complex fabricating process of a memory capacitor, thereby simplify a panel fabricating process and largely increase the aperture ratio of a pixel, by designing a control thin-film transistor to have a large parasitic capacitance between the source and the gate.
It is another object of the present invention to enable to cheaply produce a large size panel and to easily carry out a vacuum packaging that is indispensable for fabricating a field emission display by introducing glass for a substrate material instead of a conventional single crystal silicon wafer.
To achieve the object, a field emission display device in accordance with the present invention comprises an upper plate and a lower plate that are vacuum-packaged in parallel, wherein the lower plate is composed of matrix-addressable pixels, wherein the pixel formed on an insulation substrate comprises a field emitter array, a control thin-film transistor having a drain connected to the emitter electrode of the field emitter array, and an addressing thin-film transistor having a drain connected to the gate of the control thin-film transistor, wherein the field emitter array comprises a plurality of triode-type field emitters and the control thin-film transistor has a prescribed parasitic capacitance between the source and the gate enough to retain a data signal during a signal frame of the scan signal.
To achieve the object, a field emission display device in accordance with an embodiment of the present invention comprises an upper plate and a lower plate that are vacuum-packaged in parallel, wherein the lower plate comprises an insulation substrate, an emitter electrode formed on the upper part of the insulation substrate, a plurality of emitter tips formed on the emitter electrode, a gate insulation film formed apart with a certain distance from the emitter tips, the first gate formed on the gate insulation film, the second gate formed on the upper part

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