Electric lamp and discharge devices – Discharge devices having a multipointed or serrated edge...
Reexamination Certificate
2001-01-05
2004-10-26
Bruce, David V. (Department: 2882)
Electric lamp and discharge devices
Discharge devices having a multipointed or serrated edge...
C313S495000, C313S351000, C313S336000, C313S34600R, C313S310000, C445S024000
Reexamination Certificate
active
06809464
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field emission device (FED) operable at low gate turn-on voltages with high emission current densities, and a method for fabricating the FED.
2. Description of the Related Art
An FED panel with a conventional FED is illustrated in
FIG. 1. A
cathode
2
is formed over a substrate
1
with a metal such as chromium (Cr), and a resistor layer
3
is formed over the cathode
2
with an amorphous silicon. A gate insulation layer
4
with a well
4
a
, through which the bottom of the resistor layer
3
is exposed, is formed on the resistor layer
3
with an insulation material such as SiO
2
. A micro-tip
5
formed of a metal such as molybdenum (Mo) is located in the well
4
a
. A gate electrode
6
with a gate
6
a
aligned with the well
4
a
is formed on the gate insulation layer
4
. An anode
7
is located a predetermined distance above the gate electrode
6
. The gate electrode
7
is formed on the inner surface of a faceplate that forms a vacuum cavity in associated with the substrate
1
. The faceplate
8
and the substrate
1
are spaced apart from each other by a spacer (not shown), and sealed at the edges. As for color displays, a phosphor screen (not shown) is placed on or near the anode
7
.
The conventional FED emits a small amount of electrons from the micro-tip, so that a high gate voltage is required for high emission current densities. However, if the gate voltage level is beyond a predetermined voltage limit, the problems of leakage current and short life time occur. For these reasons, increasing the gate voltage is limited. As an experiment result, the frequency of arcing increases with higher gate voltage level. When an arcing occurs in the FED, damage caused by the arcing is detected at the edges of the gate
6
a
of the gate electrode
6
, wherein the gate
6
a
serves as a passageway of electrons. Also, an electrical short occurs between the anode
7
and the gate electrode
6
due to the arcing. As a result, a high anode voltage is applied to the gate electrode
6
, thereby damaging the gate insulation layer
4
below the gate electrode
6
, and the resistor layer
3
exposed through the well
4
a
. This damage is more likely caused as the gate and anode voltage levels increase.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a field emission display (FED) operable at low gate turn-on voltages with high emission current densities, and a method for fabricating the FED.
According to an aspect of the present invention, there is provided a field emission device (FED) comprising: a substrate; a cathode formed over the substrate; micro-tips having nano-sized surface features, formed on the cathode; a gate insulation layer with wells each of which a single micro-tip is located in, the gate insulation layer formed over the substrate: and a gate electrode with gates aligned with the wells such that each of the micro-tips is exposed through a corresponding gate, the gate electrode formed on the gate insulation layer.
It is preferable that a resistor layer is formed over or beneath the cathode, or resistor layers are formed both over and beneath the cathode in the FED.
According to another aspect of the present invention, there is provided a method for fabricating a field emission device (FED), comprising: forming a cathode, a gate insulation layer with wells, and a gate electrode with gates on a substrate in sequence, and forming micro-tips on the cathode exposed by the wells; forming a carbonaceous polymer layer on the gate electrode, such that the wells having the micro-tips are filled with the carbonaceous polymer layer; and etching the carbonaceous polymer layer and the surface of the micro-tips by plasma etching using a gas mixture containing O
2
for the carbonaceous polymer layer, and a gas for the micro-tips, as a reaction gas, so that the micro-tips with nano-sized surface features are formed.
It is preferable that the carbonaceous polymer layer is formed of polyimide or photoresist. The carbonaceous polymer layer may be etched by reactive ion etching (REI). The nano-sized surface features of the micro-tips can be adjusted by varying the etch rates of the carbonaceous polymer layer and the micro-tips. It is preferable that the etch rates are adjusted by varying the oxygen-to-the gas for the micro-chips in the reaction gas, plasma power, or plasma pressure during the etching process.
It is preferable that the micro-tips are formed of at least one selected from the group molybdenum (Mo), tungsten (W), silicon (Si) and diamond.
It is preferable that the reaction gas is a gas mixture of O
2
and fluorine-based gas, such as CF
4
/O
2
, SF
6
/O
2
, CHF
3
/O
2
, CF
4
/SF
6
/O
2
, CF
4
/CHF
3
/O
2
or SF
6
/CHF
3
/O
2
. Alternatively, the reaction gas may be a gas mixture of O
2
and chlorine-based gas, such Cl
2
/O
2
, CCl
4
/O
2
, or Cl
2
/CCl
4
/O
2
.
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patent: 5290610 (1994-03-01), Kane et al.
patent: 5836796 (1998-11-01), Danroc
patent: 5892321 (1999-04-01), Itoh et al.
patent: 5952987 (1999-09-01), Browning et al.
patent: 6097138 (2000-08-01), Nakamoto
patent: 6455989 (2002-09-01), Nakada et al.
patent: 6632114 (2003-10-01), Choi et al.
patent: WO 99 10974 (1999-03-01), None
patent: WO 98 21736 (1999-09-01), None
patent: WO 98 44526 (2000-01-01), None
Cha Seung-nam
Choi Jun-hee
Lee Hang-woo
Bruce David V.
Burns Doane Swecker & Mathis L.L.P.
Keaney Elizabeth
Samsung SDI & Co., Ltd.
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