Electric lamp and discharge devices – Discharge devices having a multipointed or serrated edge...
Reexamination Certificate
2002-03-28
2003-05-06
Patel, Nimeshkumar D. (Department: 2879)
Electric lamp and discharge devices
Discharge devices having a multipointed or serrated edge...
C313S336000, C313S495000
Reexamination Certificate
active
06559581
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention: The present invention relates to methods of fabricating row lines over a planarized semiconductive grid of a field emission array. Particularly, the present invention relates to row line fabrication methods that employ only two masks to define row lines and pixel openings therethrough.
Related Art: Typically, field emission displays (“FEDs”) include an array of pixels, each of which includes one or more substantially conical emitter tips. The array of pixels of a field emission display is typically referred to as a field emission array. Each of the emitter tips is electrically connected to a negative voltage source by means of a cathode conductor line, which is also typically referred to as a column line.
Another set of electrically conductive lines, which are typically referred to as row lines or as gate lines, extends over the pixels of the field emission array. Row lines typically extend across a field emission display substantially perpendicularly to the direction in which the column lines extend. Accordingly, the paths of a row line and of a column line typically cross proximate (above and below, respectively) the location of an emitter tip. The row lines of a field emission array are electrically connected to a relatively positive voltage source. Thus, as a voltage is applied across the column line and the row line, electrons are emitted by the emitter tips and accelerated through an opening in the row line.
As electrons are emitted by emitter tips and accelerate past the row line that extends over the pixel, the electrons are directed toward a corresponding pixel of a positively charged electro-luminescent panel of the field emission display, which is spaced apart from and substantially parallel to the field emission array. As electrons impact a pixel of the electro-luminescent panel, the pixel is illuminated. The degree to which the pixel is illuminated depends upon the number of electrons that impact the pixel.
An exemplary method of fabricating field emission arrays is taught in U.S. Pat. No. 5,372,973 (hereinafter “the '973 Patent”), issued to Trung T. Doan et al. on Dec. 13, 1994. The field emission array fabrication method of the '973 Patent includes an electrically conductive grid, or gate, disposed over the surface thereof and including apertures substantially above each of the emitter tips of the field emission array. Known processes, including chemical mechanical planarization (“CMP”) and a subsequent mask and etch, are employed to provide a substantially planar grid surface and to define the apertures therethrough. While the electrically conductive grid of the field emission array disclosed in the '973 Patent is fabricated from an electrically conductive material such as chromium, field emission displays that include grids of semiconductive material, such as silicon, are also known.
Typically, in fabricating row lines over planarized field emission arrays that include grids of semiconductive material, three separate mask steps and subsequent etches are employed. With reference to
FIGS. 1A and 2A
, a first mask
28
is typically required to remove semiconductive material of grid
122
from the areas between adjacent rows of emitters tips
114
and thereby define row lines
132
of the remaining portions of the semiconductive grid
122
and expose regions of dielectric layer
120
between adjacent row lines
132
.
FIGS. 1B and 2B
illustrate the use of a second mask
136
to remove conductive material
126
, which is deposited over grid
122
of semiconductive material, from the areas between adjacent row lines
132
in order to further define row lines
132
through the conductive material
126
, and from the portion of row lines
132
overlying each pixel
112
or emitter tip
114
in order to form pixel openings
140
that facilitate the travel of electrons emitted from emitter tips
114
through apertures
124
of grid
122
and past row lines
132
. With reference to
FIGS. 1C and 2C
, a third mask
150
is required to remove passivation material
134
disposed over row lines
132
from pixel openings
140
.
The use of three separate masks undesirably increases fabrication time and costs, as three separate photoresist deposition steps, three separate photoresist exposure steps, and three separate mask removal steps are required. Accordingly, row line fabrication processes that require three mask steps are somewhat inefficient.
Accordingly, there is a need for a field emission array row line fabrication method that requires fewer than three masks and, consequently, that increases the efficiency with which row lines are fabricated while reducing the likelihood of failure of the field emission arrays and the costs associated with fabricating field emission arrays.
SUMMARY OF THE INVENTION
The present invention includes a method of fabricating row lines on the planarized semiconductive grid of a field emission display. The row line fabrication method of the present invention employs two masks to define the row lines over the field emission array and pixel openings through the row lines.
According to the present invention, the column lines, emitter tips, overlying semiconductive grid, and apertures through the semiconductor grid above the emitter tips of a field emission array may be fabricated by known processes. The semiconductive grid of the field emission array may be planarized by known processes, such as by known chemical-mechanical planarization (“CMP”) techniques. Each pixel of the field emission array may include one or more emitter tips, as known in the art.
A layer of conductive material may then be deposited over the substantially planar surface of the semiconductive grid of the field emission array. A first mask, including apertures alignable between adjacent rows of pixels of the field emission array, is employed to define row lines over the field emission array. The first mask, which may be fabricated by known processes, is disposed over the layer of conductive material. The conductive material that underlies the apertures of the first mask, that is located substantially within a periphery of each of the apertures, and that is exposed through the apertures of the first mask is then removed by known techniques, such as etching. Next, portions of the semiconductive grid that underlie the apertures of the first mask and are located substantially within a periphery of each of the apertures, and that are exposed, are removed, such as by known etching techniques. These portions of the semiconductive grid may be exposed either through the apertures of the first mask or through apertures that were defined through the previously etched layer of conductive material during the removal of conductive material therefrom. As portions of the semiconductive grid of the field emission array are removed, the row lines of the field emission array are defined and the underlying layer of passivation material beneath the semiconductive grid is exposed between adjacent row lines.
A layer of passivation material is then disposed over the surface of the field emission array, including over the row lines of the field emission array. As the conductive material of the row lines and the overlying layer of passivation material are disposed over the semiconductive grid and the field emitters of the field emission array, electrons are prevented from escaping the field emission array. Accordingly, a second mask is employed to define pixel openings through the conductive material of the row lines and through the overlying layer of passivation material.
The second mask, which includes apertures that are alignable over each of the pixels of the field emission array, may be fabricated and disposed over the field emission array as known in the art. After the second mask has been disposed over the field emission array, the passivation material underlying each of the apertures, located substantially within a periphery of each of the apertures, and exposed through the apertures may be removed by known processes, such a
Guharay Karabi
Micro)n Technology, Inc.
Patel Nimeshkumar D.
TraskBritt
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