Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2002-11-19
2004-10-05
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S098000, C257S192000, C257S280000
Reexamination Certificate
active
06800878
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to field effect type compound semiconductor devices and methods for fabricating the same. More particularly, the present invention relates to a field effect type compound semiconductor device and a method for fabricating the same, wherein an etching stopper layer has a specific structure. The etching stopper layer according to the present invention can make a reduction in a temperature change &Dgr;&phgr;
B
of an electric potential barrier &phgr;
B
of a gate electrode accompanied by an etching process to form a gate recess structure in such as a HEMT (High Electron Mobility Transistor).
2. Description of the Related Art
There is a problem of an interface level in the field of an electronic device using a compound semiconductor such as GaAs or InP forming a ultra-high integrated circuit device or a high frequency amplifier element. Because of this, a field effect type compound semiconductor element such as a MESFET (Metal Semiconductor Field Effect Transistor) or the HEMT is used.
FIG. 1
is a schematically cross sectional view of a conventional HEMT.
Referring to
FIG. 1
, an i-type InAlAs buffer layer
42
is stacked on a semi-insulating GaAs substrate
41
. An i-type InGaAs electron translation layer
43
, an n-type InAlAs electron supply layer
45
, an i-type InAlP stopper etching layer
46
, and an n-type InGaAs cap layer
47
are epitaxially grown, in order, on the i-type InAlAs buffer layer
42
. After that, a source electrode
48
and a drain electrode
49
are formed by a AuGe layer and a Au layer.
A two-dimensional electron gas
44
is formed at a side of the i-type InGaAs electron translation layer
43
of an interface between the i-type InGaAs electron translation layer
43
and the n-type InAlAs electron supply layer
45
. The two-dimensional electron gas
44
is formed based on a bend of an energy band due to a difference of a forbidden band width E
g
and an electron affinity &khgr; between the i-type InGaAs electron translation layer
43
and the n-type InAlAs electron supply layer
45
.
Next, after a gate recess area is formed by a selective etching using a phosphoric acid group etchant made by H
3
PO
4
: H
2
O
2
: H
2
O, a gate electrode
50
is formed from a Ti layer, a Pt layer, and an Au layer, so that a basic structure of the HEMT can be accomplished.
In the above conventional HEMT, a GaAs buffer layer may be used as the buffer layer. An n-type AlGaAs electron supply layer may be used as a carrier supply layer.
Other than InAlP, InP having a fine etching selectivity to AlGaAs or InGaAs may be used as the etching stopper layer.
However, in a case where the etching stopper is used, as described above, in order to improve precision of forming a gate recess structure, a temperature changing ratio (&Dgr;&phgr;
B
/&phgr;
B
) of the electric potential barrier &phgr;
B
between the etching stopper layer and the gate electrode increases extremely so that operation of the semiconductor device becomes unstable. This causes a practical problem.
FIG. 2
is a view for explanation of an InAlP composition dependence of the temperature changing ratio of the electric potential barrier. That is,
FIG. 2
shows the InAlP composition dependence of the temperature changing ratio (&Dgr;&phgr;
B
/&phgr;
B
) of the electric potential barrier between room temperature and 250° C. As shown in
FIG. 2
, in a case of InP where the In composition ratio is 1.0, the electric potential barrier has a little bigger temperature changing ratio (&Dgr;&phgr;
B
/&phgr;
B
) than 22%. In addition,
FIG. 2
shows that in a case where the In composition ratio is between 0.6 and 0.7, the temperature changing ratio exceeds 40%.
Particularly, surface oxidation of Al progresses with time passing in a case of InAlP, so that a depletion layer situated at both sides of the gate electrode extends and thereby a reduction of electric current is caused on a long term basis. Because of this, reliability of the semiconductor device is deteriorated.
In addition, since fluorine group gas used in a dry etching process exists unavoidably in a manufacturing factory, F (fluorine) combines with Al on the surface of the InAlP so that an F atom diffuses to an inside of the InAlP during an operation of the device. Hence, F acts an acceptor so that a carrier is compensated.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful field effect type compound semiconductor device and method for fabricating the same in which one or more of the problems described above are eliminated.
Another and more specific object of the present invention is to effectively reduce the temperature changing of the electric potential barrier of the gate electrode.
FIG. 3
is a view of a principle structure of the present invention.
The above objects of the present invention are achieved by a field effect type compound semiconductor device, wherein at least a channel layer and an etching stopper layer are provided on a semiconductor substrate in order, a gate electrode that Schottky-contacts the etching stopper layer is provided on the etching stopper layer, and InGaP having an In composition ratio of 0.66 through 0.9 is used as the etching stopper layer.
According to the present invention as described above, the temperature changing ratio (&Dgr;&phgr;
B
/&phgr;
B
) of an electric potential barrier &phgr;
B
of the gate electrode
10
from room temperature to 250° C. becomes less than 10%. Hence, it is possible to improve reliability of the field effect type compound semiconductor device.
A cap layer
9
may be provided on the etching stopper layer
8
situated at both sides of the gate electrode
10
, and a source electrode
11
and a drain electrode
12
may be provided on the cap layer
9
.
According to the present invention as described above, it is possible to improve the ohmic performance of the source electrode
11
and the drain electrode
12
.
InGaAs may be used as the cap layer
9
.
InGaAs has a small forbidden band width and large mobility. Hence, contact resistance of the source electrode
11
and the drain electrode
12
may be further decreased.
The channel layer
3
may be a carrier translation layer, and a carrier supply layer
6
generating a two-dimensional carrier gas
4
may be provided at a side of the carrier translation layer between the carrier translation layer and the etching stopper layer
8
.
The present invention can be applied to an usual MESFET (Metal Semiconductor Field Effect Transistor, Schottky-gate field-effect transistor). It is possible to fabricate a HEMT type field effect compound semiconductor device that can operate at more high-speed, by providing the carrier supply layer
6
generating the two-dimensional carrier gas
4
at the side of the carrier translation layer.
An intermediate layer consisting of an i-type barrier layer
7
may be provided between the carrier supply layer
6
and the etching stopper layer
8
.
It is possible to assure a suitable breakdown voltage by providing the i-type barrier layer
7
. Here, the thicker the barrier layer
7
is or the wider the forbidden band width is, the more the breakdown voltage is improved.
An intermediate layer consisting of an i-type spacer layer
5
may be provided between the carrier supply layer
6
and the carrier translation layer.
It is possible to control the two-dimensional carrier gas
4
by providing the i-type spacer layer
5
. Here, the thicker the spacer layer
5
is, the higher the carrier mobility at the two-dimensional carrier gas
4
becomes and the more the sheet density of the carrier reduces.
The intermediate layer may consist of an i-type InAlAs layer having an In composition ratio of 0.3 through 0.4.
It is preferable to use the i-type InAlAs layer having the In composition ratio 0.3 through 0.4 which is lattice-matched to InGaAs having a high carrier mobility, as the intermediate layer.
The semiconductor substrate
1
and the channel layer
3
may have a lattice strain (lattice-mis
Nambu Kazuo
Nikaido Junichiro
Armstrong Kratz Quintos Hanson & Brooks, LLP
Fujitsu Quantum Devices Limited
Nguyen Dao H.
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