Field effect transistors, field effect transistor...

Details Field effect transistors, field effect transistor... Field effect transistors, field effect transistor...

2002-11-19

2004-02-17

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257S384000, C257S408000, C257S410000, C257S412000

Reexamination Certificate

active

06693313

ABSTRACT:

TECHNICAL FIELD
The invention pertains to integrated circuitry, field effect transistor assemblies, methods of forming field effect transistors, and methods of forming integrated circuitry.
BACKGROUND OF THE INVENTION
A prior art semiconductive wafer fragment
10
is shown in FIG.
1
. Wafer fragment
10
comprises a memory array region
12
and a region
14
peripheral to memory array region
12
. Wafer fragment
10
further comprises a semiconductive material substrate
16
. Substrate
16
can comprise, for example, a monocrystalline silicon wafer lightly background doped with a p-type dopant. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
A memory array transistor gate
18
is formed over memory array region
12
. Transistor gate
18
comprises a stack of materials including a gate dielectric
22
, a conductively doped polysilicon
24
, a metal silicide
26
, and an insulative cap
28
. Gate dielectric
22
can comprise, for example, silicon dioxide or tantalum pentoxide. Conductively doped polysilicon
24
can be doped to a concentration of, for example, greater than 10
19
atoms/cm
3
with either n-type or p-type conductivity enhancing dopant. Metal silicide
26
can comprise, for example, titanium silicide. Finally, insulative cap
28
can comprise, for example, silicon dioxide or silicon nitride. Alternatively, cap
28
can comprise a stack of materials including an antireflective coating and other insulative materials such as, for example, silicon nitride. The antireflective coating can comprise, for example, a deposited antireflective coating (DARC).
Sidewalls
30
are provided adjacent the transistor gate, and can comprise, for example, silicon dioxide or silicon nitride.
Source/drain regions
32
are provided within substrate
12
proximate gate
18
, and together with gate
18
form an operative field effect transistor device
33
. Source/drain regions
32
are typically doped with n-type conductivity-enhancing dopant.
A peripheral transistor gate
20
is formed over peripheral region
14
. Transistor gate
20
comprises a stack of gate dielectric
40
, conductively doped polysilicon
42
, metal silicide
44
, and an insulative cap
46
. Gate dielectric
40
, conductively doped polysilicon
42
, silicide
44
and insulative cap
46
can comprise materials such as those discussed above pertaining to gate dielectric
22
, conductively doped polysilicon
24
, silicide
26
and cap
28
, respectively.
Sidewalls
48
are provided adjacent gate stack
20
, and source/drain regions
50
are provided within substrate
16
proximate to gate stack
20
. Source/drain regions
50
and gate stack
20
together form a functional field effect transistor
53
. Source/drain regions
50
can be doped with p-type conductivity enhancing dopant or n-type conductivity enhancing dopant to form either a p-type metal-oxide semiconductor (PMOS) or n-type metal-oxide semiconductor (NMOS) transistor. Such transistor can be incorporated into, for example, complementary metal-oxide semiconductor (CMOS) circuitry.
The functions of transistors
33
and
53
are different, and accordingly problems associated with gates
18
and
20
can be somewhat different. For instance, a problem associated with transistor gates in a memory array (such as, for example, a dynamic random access memory (DRAM) array) is leakage current between source and drain regions, and a problem associated with peripheral transistor gates is the speed of a change from an off-current to an on-current. The above-mentioned problems can be differently affected by a thickness of a gate dielectric material. Accordingly, there has been an effort to vary the thickness of dielectric material
40
of the peripheral transistor
53
relative to the thickness of dielectric material
22
of memory array transistor
33
. Ideally, dielectric material
22
would be as thin as possible, and dielectric material
40
would be somewhat thicker. Presently, dielectric materials can be formed to thicknesses of as little as about 50 Angstroms, but it has proved difficult to reliably form the materials thinner than 50 Angstroms. Such difficulty results from the inherent size and spacing of atoms. For instance, a silicon structure will typically have about a 5.3 Angstrom separation between atoms. Accordingly, a gate dielectric comprising silicon and which is 50 Angstroms thick will have a maximum of 10 monolayers of silicon atoms. Thus, even small inhomogeneities within or between the monolayers can significantly impact the uniformity of a material comprising the layers, and accordingly destroy device operation of transistor gate devices formed utilizing such material.
It would be desirable to develop alternative methods and structures for controlling physical and electrical properties of transistor gates.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses integrated circuitry. Such circuitry includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a first layer of conductively doped semiconductive material and only one layer of conductive nitride. The integrated circuitry further comprises a second field effect transistor supported by the substrate. The second field effect transistor comprises a second transistor gate assembly which includes a second layer of conductively doped semiconductor material and at least two layers of conductive nitride.
In another aspect, the invention encompasses a field effect transistor assembly. Such assembly includes a substrate and source/drain regions supported by the substrate. A channel region is defined between the source/drain regions, and the transistor assembly includes an insulative material along the channel region. The transistor assembly further includes a gate stack proximate the channel region. The gate stack includes a first conductive nitride layer separated from the channel region by the insulative material. The stack further includes a conductively doped semiconductive material proximate the first conductive nitride layer, and a second conductive nitride layer separated from the first conductive nitride layer by the conductively doped semiconductive material.
In yet other aspects, the invention encompasses methods of forming field effect transistors, and methods of forming integrated circuitry.


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“The effect of impurities in TiN film when used as MOS gate electrodes”; Yang, H.; Hu et al.; Conference: Advanced Interconnects and Contact Materials and Processes for Future Integrated Circuits, Symposium, p. 343; Publisher: Mater. Res. Soc., Warrendale, PA 1998.
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