Field effect transistor with lightly doped drain structure and m

Details Field effect transistor with lightly doped drain structure and m Field effect transistor with lightly doped drain structure and m

1987-03-25

1991-10-29

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 40, 437 41, 437154, 357 233, 357 234, H01L 21265

Patent

active

050616498

ABSTRACT:
A semiconductor integrated circuit device is disclosed which has an MOSFET with a lightly doped drain or LLD structure. A gate electrode layer is insulatively provided above a semiconductor substrate of p conductivity type. Source and drain layers of n conductivity type are formed in the substrate in such a manner as to be substantially self-aligned with the gate electrode. Each of these source and drain layers is comprised of a heavily doped diffusion layer and a lightly doped diffusion layer. The n- diffusion layer is deep enough to fully surround the heavily doped layer in the substrate. The n- diffusion layer has a step-like cross-section, whereby the effective channel length of MOSFET is increased inside the substrate to increase the punch-through voltage level.

REFERENCES:
patent: 4172260 (1979-10-01), Okabe et al.
patent: 4356623 (1982-11-01), Hunter
patent: 4613882 (1986-09-01), Pimbley et al.
patent: 4680603 (1987-07-01), Wei et al.
patent: 4746624 (1988-05-01), Cham et al.
Grinolds et al., "Reliability and Performance of Submicron LDD MOSFETs' with Buried-As N-Impurity Profiles", IEDM 12/1985, pp. 246-249.
Wada et al., "A Study of Hot-Carrier Degradation in Optimized 1 .mu.m LDD-MOSFET Using Device Simulator", presented at the 45th Japanese Applied Physics Conference, Oct. 12-15, 1984.

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