Field effect transistor with lightly doped drain regions

Details Field effect transistor with lightly doped drain regions Field effect transistor with lightly doped drain regions

1995-09-12

1997-09-30

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

257194, 257280, 257285, 257287, H01L 310328, H01L 310336, H01L 31072, H01L 31109

Patent

active

056728905

ABSTRACT:
It is an object of the present invention to provide a structure of a field effect transistor, which effectively suppresses a leakage current from a source/drain region to a substrate side without increasing a parasitic capacitance, and a method of manufacturing the same. According to the present invention, when an LDD structure is to be constituted by forming, in a semiconductor substrate, an active layer of a first conductivity type, a heavily doped layer of the first conductivity type, which is separated from the active layer by a predetermined distance and has a high impurity concentration; and an intermediate concentration layer of the first conductivity type, which is formed between the active layer and the heavily doped layer and has an impurity concentration lower than that of the heavily doped layer, regions of a second conductivity (these regions are converted into depletion layers upon contact with the corresponding regions of the first conductivity), which cover the entire bottom portion of the corresponding region are formed.

REFERENCES:
patent: 4962054 (1990-10-01), Shikata
patent: 5124770 (1992-06-01), Umemoto
patent: 5182218 (1993-01-01), Fujihira
English Abstract for Japanese Patent No. 63-124471.
English Abstract for Japanese Patent No. 63-281470.

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