Field effect transistor with integrated schottky diode clamp

Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – To compound semiconductor

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257280, 257281, 257486, H01L 2980, H01L 27095, H01L 2947

Patent

active

055258298

ABSTRACT:
A MOSFET device is constructed with an integrated Schottky diode clamp connected between the source or drain terminal and the bulk terminal. In an illustrative implementation, one or more MOSFETs are formed in an n-well located in a p-type silicon substrate. Each drain is formed by a p+ region underlying a portion of a metal-silicide layer. In one embodiment, the p+ region underlies an edge of the metal-silicide; in another embodiment, the p+ region underlies opposing edges of the metal-silicide, such that a portion of the metal-silicide contacts the n-well. Each source is formed by a p+ region underlying a layer of metal-silicide. Each gate includes a layer of p+ or n+ polycrystalline silicon clad with a layer of metal-silicide, the gates being separated from the n-well by a layer of oxide. In comparison to p-n junction diodes, the integrated Schottky diodes more effectively limit excess voltages applied to MOSFETs. The clamping performed by the invention reduces wearout and other deleterious effects of excess voltage.

REFERENCES:
patent: 3617824 (1971-11-01), Shinoda et al.
patent: 4288371 (1980-10-01), Mazgy
patent: 4365171 (1982-12-01), Archer
patent: 4492974 (1985-01-01), Yoshida et al.
patent: 4513309 (1985-04-01), Cricchi
patent: 4709251 (1987-11-01), Suzuki
patent: 4801983 (1989-01-01), Ueno et al.
patent: 4835580 (1989-05-01), Havemann et al.
patent: 4963970 (1990-10-01), Throngunumchai
patent: 4982244 (1991-01-01), Kapoor
patent: 5177568 (1993-01-01), Honma et al.
J. Sanchez et al., "Drain-Engineered Hot-Electron-Resistant Device Structures: A Review", IEEE Trans. on Elect. Dev., vol. 36, No. 6, pp. 1125-1132, Jun. 1989, place of publication unknown.
C. Hu et al., "Hot-Electron-Induced MOSFET Degradation--Model, Monitor, and Improvement," IEEE Journal of Solid-State Circuits, vol. SC-20, No. 1, Feb. 1985, pp. 295-305, place of publication unknown.
"Prevention of CMOS Circuit Latch-Up", IBM Technical Disclosure Bulletin, vol. 29, No. 5, Oct., 1986, New York, US p. 1967
Patent Abstracts of Japan vol. 8, No. 21 (E-224) 28 Jan. 1984 & JP-A-58 182 871 (Tokyo Shibaura Denki) 25 Oct. 1983.
Yang et al. "Silicide Doping Technology in Formation of TiSi2/N+P Shallow Junction by Salicide Process" Journal of Applied Physics vol. 65, No. 3, 1 Feb. 1989, New York US, pp. 1039-1043.
"Lightly Doped Drain Structure with Reduced Series Resistance to Device Channel" IBM Technical Disclosure Bulletin vol. 32, No. 3A, Aug. 1989, New York, US pp. 485-486.

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