Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
1999-07-12
2001-06-26
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S774000
Reexamination Certificate
active
06252266
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device employing a field-effect transistor having a gate electrode with a comb-shaped structure and, more particularly, to the semiconductor device having a structure designed to minimize a reduction in gain in a high frequency band not lower than the microwave band.
2. Description of the Prior Art
An example of the prior art field-effect transistor having a gate electrode with a comb-shaped structure is shown in FIG.
19
. Referring to
FIG. 19
, the field-effect transistor (or the FET)
200
to be used at a high frequency higher than the microwave band is provided with a gate electrode
201
having a comb-shaped structure, a drain electrode
202
similarly having a comb-shaped structure and an array of source electrodes
204
that are connected together by way of an air bridge
203
. The source electrodes located at both ends of the array of the source electrodes
204
are connected to corresponding grounding electrodes
206
a
and
206
b
grounded by way of via holes
205
a
and
205
b.
A semiconductor chip having the FET
200
formed thereon has test electrodes
210
a,
210
b,
220
a
and
220
b
formed thereon that are used during a on-wafer examination to determine operating characteristics of the FET
200
on the wafer. The test electrodes
210
a,
210
b
,
220
a
and
220
b
are connected in correspondence with test pads
211
a,
211
b,
221
a
and
221
b,
respectively, that are used for connection with a test machine during the on-wafer examination.
The test pads
211
a
,
211
b
,
221
a
and
221
b
are connected to the ground through the corresponding via holes
212
a
,
212
b
,
222
a
and
222
b
. A high frequency signal inputted from an external circuit by way of a connection pad
213
, formed between the test pads
211
a
and
211
b,
during the on-wafer examination is inputted to the gate electrode
201
through a signal line
214
. The high frequency signal inputted is amplified by the FET
200
, and the amplified high frequency signal is outputted from a connection pad
223
, formed between the test pads
221
a
and
221
b,
through the drain electrode
202
by way of a signal line
224
. The connection pads
213
and
223
are connected with an external circuit when the FET
200
available as a commercial product is used.
In the above construction, the field-effect transistor
200
has a parasitic impedance comprised of a source resistance Rs and a parasitic inductance (referred to as a source inductance hereinafter) Ls on the source electrode side, which are generated due to the structure of the source electrodes, the grounding electrodes and the via holes.
FIG. 20
is a graph showing a relation between a unit gate width Wgu and a total gate width Wgt of the gate electrode
201
with respect to the source inductance Ls of the FET
200
shown in FIG.
19
.
FIG. 20
shows the fact that the source inductance Ls increases according to a reduction in the unit gate width Wgu and an increase in the total gate width Wgt.
On the other hand,
FIG. 21
illustrates an equivalent circuit of the FET
200
during the on-wafer examination. As shown therein, during the on-wafer examination, in addition to the source inductance Ls, a parasitic impedance Lt is also generated due to the structure of the test electrodes
210
a,
210
b
,
220
a
and
220
b
and the via holes
212
a
,
212
b
,
222
a
and
222
b
. Reference character Rs used in
FIG. 21
represents a source resistance of the FET
200
.
As described above, there has been the conventional problem that the gain of the FET
200
reduces to deteriorate the high-frequency characteristics because of the increase in frequency and the increase in the parasitic impedance accompanying the increase in the total gate width of the FET
200
. This has resulted in a difficulty in obtaining both a high gain and a large output power in the high frequency band with the prior art FET
200
having the comb-shaped gate structure.
It is to be noted that a field-effect transistor in which the source inductance of the via holes is reduced by arranging a plurality of via holes in a source electrode pad is disclosed in, for example, Japanese Patent Laid-Open Publication No. 8-274116.
SUMMARY OF THE INVENTION
The present invention has been made to solve the aforementioned problems and has the object of obtaining a semiconductor device employing an field-effect transistor which can prevent a reduction in gain in a high frequency band higher than the microwave band attributed to an increase in the total gate width, to thereby improve the high-frequency characteristics by reducing the parasitic impedance and which is effective to increase the accuracy of various measurements conducted during the on-wafer examination.
In order to achieve this object, there is provided a semiconductor device employing a field-effect transistor which has a gate electrode and a drain electrode of a comb-shaped structure and in which a plurality of source electrodes arranged in an identical axis are connected together by way of a conductor, the semiconductor device comprising via holes for grounding corresponding grounding electrodes connected to corresponding source electrodes located in both end positions of the source electrodes, the via holes each having an elliptical shape.
By virtue of the elliptical shape of the via holes, a distance from the source electrode connected to the grounding electrode to a signal transmission path in the via hole can be reduced, and the signal transmission path in the via hole increased. Therefore, the parasitic inductance of the via holes can be reduced and the parasitic impedance ascribed to the grounding of the source electrodes by means of the grounding electrodes and the via holes can be reduced, so that a high-frequency characteristic deterioration such as a reduction in gain in a high frequency band higher than the microwave band can be prevented.
According to another aspect of the present invention, there is provided a semiconductor device employing a field-effect transistor which has a gate electrode and a drain electrode of a comb-shaped structure and in which a plurality of source electrodes arranged in an identical axis are connected together by way of a conductor, wherein grounding electrodes connected to corresponding source electrodes located in both end positions of the source electrodes are grounded by way of a plurality of via holes. With this arrangement, the parasitic inductance of the via holes can be totally reduced. Therefore, the parasitic impedance ascribed to the grounding of the source electrodes by means of the grounding electrodes and the via holes can be reduced, so that a high-frequency characteristic deterioration such as a reduction in gain in a high frequency band higher than the microwave band can be prevented.
It is preferred that the via holes provided in correspondence with the respective grounding electrodes should be arranged in positions symmetrical about the axis of the array of the source electrodes. With this arrangement, the parasitic inductance of the via holes can be further reduced. Therefore, the parasitic impedance ascribed to the grounding of the source electrodes by means of the grounding electrodes and the via holes can be further reduced, so that a high-frequency characteristic deterioration such as a reduction in gain in a high frequency band not lower than the microwave band can be more surely prevented.
It is preferred that at least one of the via holes provided for one grounding electrode should be arranged in the vicinity of the drain electrode and/or the gate electrode while being not put in contact with the electrodes, and an end portion that belongs to the grounding electrode and is located close to the via hole arranged in the vicinity of the drain electrode and/or the gate electrode should be connected to the nearby source electrode by means of a conductor. In this case, the parasitic inductance component of the conductor included in the source inductance of the
Hoshi Hiroyuki
Kurusu Hitoshi
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
Munson Gene M.
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