Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
1999-11-12
2002-11-05
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S192000, C257S194000, C257S195000, C257S276000
Reexamination Certificate
active
06476431
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field effect transistor and a method for manufacturing the same, and more particularly to a structure of a device and a transistor which endures a high tolerance voltage and which allows a large amount of current to flow and a method for manufacturing the device or the transistor.
2. Description of the Related Art
As a device which has a high tolerance voltage such as silicon devices, there are known a VMOS (V-grooved Metal Oxide Semiconductor) transistor and a VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) transistor which are referred to as a vertical structure type transistor, and a RESURF (Reduced Surface Field) structure transistor or an L-DMOS (Lateral Double-Diffused Metal Oxide Semiconductor) transistor which are referred to as a horizontal structure type transistor. These devices and transistors are described in the “Modeling of the On-Resistance of LDMOS, VDMOS and VMOS Power Transistors” (IEEE Trans. on Electron Devices, Vol. ED-27, p356), a document published by S. C. Sun and J. D. Plummer in 1980. These transistors are characterized in that they have a high concentration p-type layer under the gate and a region named a drift layer provided between the gate and the drain in addition to the normal transistor structure. On the drift layer, a channel comprising an n-type conductive, and a metal electrode fixed to the source potential in parallel with the channel are provided on the surface of the substrate via an oxide film, or a p-type layer is provided in the substrate.
A breakdown of the power-FET which is caused by a voltage exceeding a tolerance voltage is finally determined by the fact that an electron current further increases by a positive return such that an increase in the electron current, the generation of holes (positive holes) by avalanche breakdown, the excitation of electrons by the positive carrier (holes) allows a destructive current to flow. The p-type layer immediately under the gate works in the same way as the channel dope layer used for the suppression of the short channel effect with a fine MOSFET. As a consequence, the leak current decreases in the OFF state of the transistor, and the avalanche breakdown caused by the seed of this leak current is not generated so that the generation of the holes is suppressed. The effect of the p-type layer which decreases the seed current of the avalanche breakdown contributes conspicuously toward an improvement in the tolerance voltage.
Since no depletion layer spreads in the n-type layer at a low drain voltage in the drift layer, the channel of the n-type layer has a low resistance. On the other hand, a large bias is applied between the n-type layer, and the p-type layer or a metal electrode at a high drain voltage with the result that the n-type layer is depleted. As a consequence, the n-type layer can serve as a high resistor. When the n-type channel is completely depleted, a uniform electric field is applied in the direction of the channel so that no concentration of the electric field is generated. Consequently, the avalanche breakdown is hardly generated and a high-tolerance voltage is provided. When the drift layer is set to a five-pole tube mode, the same effect as the cuss code connection at the so-called two FET with the result that a high frequency characteristic is not damaged.
However, in a compound semiconductor power-FET, no such drift layer is provided. This is because the compound semiconductor has a high surface state level unlike silicon with the result that this surface state level serves as the same function as the p-type layer, and it was not required to actively introduce the p-type layer. However, since the surface state level which serves in the same way as the p-type layer is formed with the implantation of the negative carrier from the gate electrode, the length of the surface state level is definite. The length of the surface state level does not stand in proportion to the distance between the gate and the drain like the drift layer described above, and the tolerance voltage is limited to about 20V.
Thus, in order to enhance the tolerance voltage, an attempt has been made to introduce the p-type layer in the same manner as the silicon device for the suppression of the short channel effect and for an effective operation of the drift layer. In the case where a transistor is formed on the semi-insulation substrate, the p-type layer is surrounded with the semi-insulation substrate and the non-doped layer with the result that the p-type layer is electrically drifted. However, in the case where the generation of the holes at the avalanche breakdown is small in amount, the potential of the p-type layer leads to the formation of p-n junction with the n-type layer of the source and the drain. Thus, the source side with a low voltage constitutes a normal direction junction so that the potential of the p-type layer becomes approximately equal to the source potential. In such a case, with the same mechanism with the case of the MOSFET, the tolerance voltage has improved in the OFF state in which the drain current does not flow.
However, when the drain voltage is allowed to be increased in the ON state, a permanent breakdown which invites the thermal breakdown is generated at a relatively low voltage. The cause of the permanent breakdown can be described as follows. In other words, at a high voltage more than a certain degree accompanied by the flow of the drain current, the holes begin to be generated resulting from the avalanche breakdown. When the holes are accumulated in the vicinity of the channel, the positive voltage is generated which invites an increase in the drain current. As a consequence, the positive return of a current increase which has been described before is generated which leads to the permanent breakdown. When the current begins to flow through the FET, the electric field is concentrated on the drain end in a channel having a uniform doping with the result that the generation of a high electric field can not be avoided in the ON state. As a consequence, virtually no effect on the tolerance voltage is generated with the introduction of the p-type layer buffer which is drifting. Consequently, a high-tolerance voltage operation on the order of several hundred Volts which is obtained in the silicon MOSFET cannot be obtained.
Furthermore, actually, in the power-FET, B class or AB class operation amplifiers are used in many cases in order to realize a higher efficiency. In the case of such operation mode, the gate voltage in the half period of the input AC signal, the gate voltage will be lowered to a level lower than the level of the voltage at which the channel is temporarily cut off. When the gate voltage is lowered to a negative voltage, the n-type channel which constitutes a barrier of the holes is depleted and the p-type layer hole flows into the gate over the channel portion. On the other hand, an opposite bias is applied in the half period, but the holes are not implanted into the channel because the gate is a shot key electrode, and only the electrons of the channel flow into the gate. As a consequence, the flow of the holes as a whole is directed only in one direction with the result that the p-type layer holes is pulled out in a one-sided manner. In the case where the p-type layer is electrically drifted from the other electrode, the potential of the p-type layer is lowered. The drift current is lowered in the same manner as at the time when a negative substrate bias is applied with the result that a large electric power cannot be generated.
Furthermore, in the drifting p-type layer, a similar decrease in the drain current is generated in another mechanism. In the power-FET, the drain voltage is largely changed. As a consequence, the potential of the drifting p-type layer is oscillated with the capacity junction with the drain and the channel. In a normal state, as has been described above, the potential of the p-type layer is approximate to the source potential. Howe
Kasahara Kensuke
Kunihiro Kazuaki
Ohno Yasuo
Takahashi Yuji
Loke Steven
McGinn & Gibb PLLC
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