Field effect transistor structure with self-aligned raised...

Details Field effect transistor structure with self-aligned raised... Field effect transistor structure with self-aligned raised...

2002-07-30

2004-04-06

Coleman, W. David (Department: 2823)

Electrical connectors

Coupling part having handle or means to move contact...

Movable latching prong or latch on prong

C438S278000, C438S585000, C438S587000

Reexamination Certificate

active

06716046

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to metal-oxide-semiconductor field effect transistors (MOSFETs) and more particularly to transistor structures having self-aligned raised source/drain regions, and methods of making same.
2. Background
The trend of integrating more functions on a single substrate while operating at ever higher frequencies has existed in the semiconductor industry for many years. Advances in both semiconductor process technology and digital system architecture have aided in producing these more highly integrated and faster operating integrated circuits.
The desired result of many recent advances in semiconductor process technology has been to reduce the dimensions of the transistors used to form the individual circuits found on integrated circuits. There are several well-recognized benefits of reducing the size of transistors. In the case of MOSFETs, reducing the channel length provides the capability to deliver a given amount of drive current with a smaller channel width. By reducing the width and length of a FET, the parasitic gate capacitance, which is a function of the area defined by the width and length can be reduced, thereby improving circuit performance. Similarly, reducing the size of transistors is beneficial in that less area is consumed for a given circuit, and this allows more circuits in a given area, or a smaller, less costly chip, or both.
It has also been well known that MOSFETs can not simply be scaled down linearly. That is, as the width and length attributes of a MOSFET are reduced, other parts of the transistor, such as the gate dielectric and the junctions must also be scaled so as to achieve the desired electrical characteristics. Undesirable electrical characteristics in MOSFETs due to improper scaling include coupling of the electric field into the channel region and increased subthreshold conduction. These effects are sometimes referred to in this field as short channel effects.
A number of methods have been developed to form ever more shallow source/drain junctions for MOSFETs in order to achieve proper scaling. Unfortunately, these very shallow junctions create source/drain extensions that have increased resistivity as compared with deeper source/drain junctions. In longer channel length MOSFETs with deeper source/drain junctions, the source/drain extension resistivity was negligible compared to the on-resistance of the MOSFET itself. However, as MOSFET channel lengths decrease into the deep sub-micron region, the increased source/drain extension resistivity becomes a significant performance limitation.
What is needed is a field effect transistor structure having very short channel length and low source/drain extension resistivity, yet operable to produce high drive currents without suffering from the short channel effects that produce significant levels of off-state current. What is further needed is a method of manufacturing such a structure.
SUMMARY OF THE INVENTION
Briefly, field effect transistor structures include a channel regions formed in a recessed portion of a substrate. The recessed channel portion permits the use of relatively thicker source/drain regions thereby providing lower source/drain extension resistivity while maintaining the physical separation needed to overcome various short channel effects.
In a further aspect of the present invention, the surface of the recessed channel portion may be of a rectangular, polygonal, or curvilinear shape.


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