Field effect transistor structure with bent gate

Details Field effect transistor structure with bent gate Field effect transistor structure with bent gate

2000-07-11

2004-03-30

Fahmy, Wael (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S275000, C257S712000, C257S713000

Reexamination Certificate

active

06713793

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical field of the Invention
The present invention relates to a semiconductor device, particularly an inexpensive, small-sized and high-output semiconductor device, and a process for manufacturing the same.
2. Description of Related Arts
Field-effect transistors (FET) using compound semiconductors such as gallium arsenide (GaAs) and the like have been conventionally used as the main devices of equipment for use in satellite and mobile communications because of their high frequency and high output characteristics. With the recent drastic advance in information technology, further improvement in performance, cost and size are demanded for FETs.
FIGS. 17 and 18
show a conventional discrete type high-output multi-finger FET chip (
200
) for use in a transmission amplifier for mobile communication. The FET chip (
200
) has a rectangular substrate (
202
) formed of semi-insulating gallium arsenide. An insulating region (
204
) and an active region (
206
), not overlapped on each other, are formed on one surface of the substrate (
202
) (the upper side in FIG.
18
). A number of FET elements (hereinafter referred to as “FET units”) are formed on the active region (
206
). The FET unit includes a narrow gate a electrode (
208
) which extends parallel to the direction of the shorter edge of the FET chip (
200
) (in the Y-axial direction in FIG.
17
), a source wire (
210
) and a drain wire (
212
). The gate electrode (
208
) is directly formed at a regular interval on the substrate (
202
). On the other hand, the source wire (
210
) and the drain wire (
212
) are arranged on the substrate (
202
) through a source electrode (
226
) and a drain electrode (
228
), respectively, and the source wire (
210
) and the drain wire (
212
) are opposed to each other through the gate electrode (
208
).
The gate electrode (
208
) is electrically connected to a gate feeder (
222
) which is arranged along the longer edge of the substrate (
202
). The gate feeder (
222
) is electrically connected to a gate pad (
214
) which is arranged on a portion of the insulating region adjacent to one of the longer edges of the substrate (
202
). A source pad (
216
) is arranged between each of adjacent gate pads (
214
). The source pad (
216
) and the source wire (
210
) are electrically connected to each other through an air bridge (
210
f
) which is located therebetween above the gate feeder (
222
). On the other hand, the drain wire (
212
) is electrically connected to a drain pad (
218
) which is arranged on a portion of the insulating region adjacent to another longer edge of the substrate (
202
).
A via-hole (
220
) penetrating the substrate (
202
) is formed in each of the source pads (
216
), and through this via-hole (
220
), each of the source pads (
216
) is electrically connected to a gold plated layer (
232
) on the other side of the substrate (
202
).
In the FET chip (
200
) thus constructed, a current supplied to the source pad (
216
) passes through the source wire (
210
), the source electrode (
226
), a portion of the active layer adjacent to the gate electrode (
208
), namely a channel (
230
), the next drain electrode (
228
), and further the drain pad (
218
) through the drain wire (
212
). At this stage, by increasing or decreasing the voltage applied to the gate electrode (
208
), the current flowing from the source pad (
216
) to the drain pad (
218
) can be varied.
The FET chip (
200
) also has a plurality of gate electrodes (
208
) which are arranged in parallel. The total width of the plurality of gate electrodes (
208
) is very wide, so that the FET chip (
200
) can generate high output when a great amount of current is allowed to pass therethrough.
Specifically, the FET chip (
200
) shown in
FIG. 17
is used an amplifier of a frequency of 1 to 2 GHz and an output power of 100 watts. In this case, each of the gate electrodes (
208
) is about 900 &mgr;m in width. There are arranged one hundred gate electrodes (
208
), and thus, the total width of the gate electrodes (the length of the gate layer) is about 100 mm.
FIGS. 19 and 20
show a high output FET chip (
250
) having a source island via-hole (SIV) structure provided with a heat sink. In this FET chip (
250
), two source electrodes (
226
) are arranged in parallel between each of adjacent gate electrodes (
208
). A slot-like via-hole (
220
) is formed between two source electrodes (
226
) A parallel thereto, and through this via-hole (
220
), the two source electrodes (
226
) are electrically connected to a gold plated layer (
232
) which is provided on the reverse surface of the substrate (
202
) as a heat sink for releasing heat.
The gold plating layer (
232
) can be used as an earth electrode. In this case, the distance between the source electrode (
226
) and the earth becomes shorter, so that the parasitic inductance is decreased. Therefore, the FET chip (
250
) is particularly suited for use in a high frequency range.
It is needed to increase the drain current and/or to improve the withstand voltage of the FET chip (
200
) between the gate and the drain in order to enhance the output features of the foregoing FET chip (
200
). The withstanding voltage between the gate and the drain varies depending upon the withstanding voltage of each of the FET units. On the other hand, in order to increase the drain current, it is necessary to increase the total width of the gate electrodes. Then, in order to increase the total width of the gate electrodes, it is necessary to increase the number of FET units and the width of the gate electrode of the FET units. In this case, there arises a new problem in that the size of the FET chip becomes larger.
There are several restrictions in decreasing the size of the FET chip. This will be described in detail hereinafter. A large current flows between the source and the drain. For example, during an operation, alternating current flows between the source and the drain, and an average current per unit width of the gate is about 200 mA/mm, and the maximal current is larger than the average current. To allow the maximal current to flow, certain widths are needed between the source electrode (
226
) and the drain electrode (
228
), and between the source wire (
210
) and the drain wire (
212
).
However, the FET chip (
200
) shown in
FIGS. 17 and 18
has a problem in that, while it is possible to allow a comparatively large current to flow to the source wire (
210
) in contact with the source electrode (
226
) and to the drain wire (
212
) in contact with the drain electrode (
228
), there is a limit, to the current which flows to the air bridge (
210
f
) because the section of the air bridge (
210
f
) for connecting the source wire (
212
) to the source pad (
216
) is small. Therefore, the allowable current of the FET chip (
200
) is determined depending on the allowable current of the air bridge (
210
f
).
In addition, the thickness of the air bridge (
210
f
) is as comparatively high as several micrometers. Therefore, it is difficult to narrow the interval between each of adjacent air bridges (
210
f
) (in other words, to increase the width of the air bridge (
210
f
)) when the thickness of a photoresist layer for forming the air bridge (
210
f
) is increased. For this reason, it is not easy to narrow the width of the FET chip (
200
) in the X-axis direction in FIG.
17
.
Also, the FET chip (
250
) shown in
FIGS. 19 and 20
has the following problem. As mentioned above, a via-hole (
210
) is located between a pair of source electrodes (
226
). In order to form such a via-hole (
210
), it is necessary for the FET chip (
250
) to have a certain length in the X-axis direction in FIG.
20
. Therefore, to achieve high output from the FET chip (
250
), the FET chip (
250
) must have a at certain length in the X-axis direction. Thus, there is a limit to decreasing the length of the FET chip in the X-axis direction.
In this regard, the high output FETs having heat sink structures are already described in Japanese Kokoku Patent Publication Nos. 7-77265 and 8-21598. Howev

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