Field effect transistor structure with an insulating layer...

Details Field effect transistor structure with an insulating layer... Field effect transistor structure with an insulating layer...

2011-04-12

2011-04-12

Tran, Minh-Loan T (Department: 2826)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C257S408000, C257SE21431, C257SE29266, C257SE21619, C257SE21634, C257S344000

Reexamination Certificate

active

07923346

ABSTRACT:
A method of making a FET includes forming a gate structure (18), then etching cavities on either side. A SiGe layer (22) is then deposited on the substrate (10) in the cavities, followed by an Si layer (24). A selective etch is then carried out to etch away the SiGe (22) except for a part of the layer under the gate structure (18), and oxide (28) is grown to fill the resulting gap. SiGe source and drains are then deposited in the cavities. The oxide (28) can reduce junction leakage current.

REFERENCES:
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patent: 2004/0038533 (2004-02-01), Liang
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patent: 2005/0173735 (2005-08-01), Li
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patent: 2005/0285193 (2005-12-01), Lee et al.
Jurczak, M; et al “Dielectric Pockets—A New Concept of the Junctions for DECA-Nanometric CMOS Devices” IEEE Transactions on Electron Devices, vol. 48, No. 8, Aug. 2001, pp. 1770-1775.

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