Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – To compound semiconductor
Reexamination Certificate
1999-09-08
2003-09-09
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
To compound semiconductor
C257S473000, C257S570000
Reexamination Certificate
active
06617660
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a field effect transistor semiconductor, more particularly relates to a structure of a gate electrode of the field effect transistor using a GaAs substrate and a method for manufacturing the same.
2. Description of the prior art
Various self-alignment processes for a metal semiconductor field effect transistor (herein after referred as a MESFET) using a GaAs substrate etc. have been developed to improve an accuracy of a gate length and obtain such as lower source resistance by avoiding possible effects from a surface depletion layer. Explanation will be made, with reference to
FIGS. 5A
to
5
F, on a self-alignment process using a dummy gate when a GaAs epitaxial semiconductor substrate is used.
A silicon nitride (SiN) protection film
102
of 50 nm in thick is formed on a GaAs epitaxial semiconductor substrate
101
having a channel layer by an ECR (electron cyclotron resonance) plasma CVD (chemical vapor deposition) method. A dummy gate
103
is formed on the SiN protection film
102
by photoresist and an n
+
layer
104
is formed by self-align ion-implantation (see FIG.
5
A).
Then, the width of the dummy gate
103
is reduced by oxygen plasma to shorten the length of the dummy gate (see FIG.
5
B). As found from the subsequent processes, this process defines a distance between a gate electrode end and an n
+
layer
104
. Generally, in a case of a GaAs MESFET, the distance of about 200-500 nm is often applied.
Then, a silicon oxide (SiO
2
) layer
105
as an insulating film is deposited by an ECR plasma CVD method and the SiO
2
layer adhering only to a side wall of the dummy gate
103
is selectively etched (see FIG.
5
C).
Further, a gate pattern is formed by a lift-off method, and is annealed by a rapid thermal process (see FIG.
5
D).
A source/drain electrode
106
containing a laminated metallic layer of AuGe (gold, germanium)/Ni (nickel)/Au (gold) and a gate electrode
107
containing a laminated metallic layer of Pt (platinum)/Ti (titan)/Pd (paradium)/Au (gold) are formed by photoresist patterning technique (see FIG.
5
E).
After forming a protecting film
108
for purposes of moisture protection etc. and a contact hole, an electrode
109
to be in contact with an external bias is formed by patterning technique (see FIG.
5
F).
In the above GaAsMESFET, a schottky barrier potential in a case where Pt is in schottky contact with the GaAs substrate is higher than in case of Al or Ti. Therefore, an allowable range of a forward voltage applied to the gate electrode
107
of the MESFET can be extended and a large input signal can be input to the MESFET. Thus, when it is used as a power amplifier, a great amount of output power can be obtained. Furthermore, when Pt etc. is embedded by heat treatment, a thickness of a channel layer at both sides of the gate can be greater than that at a part of the channel layer beneath the embedded gate. Thus, parasitic resistance occurred in this area can be restrained and transconductance gm of the Field effect transistor can be improved. In addition, embedded gate structure can improve mechanical adhisiveness to the GaAs substrate.
As shown in
FIG. 6
, the above MESFET has a gate metal
107
further extended except for the regions being in contact with the semiconductor, and has an advantage of reducing the gate metal resistance. However, when Pt and Pd are used for gate electrode material, Pt and Pd do not adhere fixedly to the insulating film
105
containing SiO
2
layer. As a result, the gate metal on the insulating film
105
is stripped and torn off soon after the gate electrode
107
is formed. This problem can not be solved even when the heat treatment is applied. Thus, the characteristics become degraded due to the increase of gate resistance and the production yield is reduced.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above conventional problem and has an objective to provide the field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve the production yield thereof.
The field effect transistor semiconductor in this invention comprises a source/drain electrode positioned in a predetermined position in a semiconductor substrate, a channel region provided in the semiconductor substrate and between the source/drain electrodes, a gate electrode which is in schottky contact with a part of a channel region and is positioned between the source/drain electrodes, an insulating film which electrically insulates a surface of the semiconductor substrate and the gate electrode at both side surfaces of the gate electrode. And the gate electrode covers a part of the insulating film and the surface of the substrate serving as the channel region, and a bottom metallic layer contained in the gate electrode is covered with a second metallic layer which is highly adhesive to the insulating film.
The bottom metallic layer may contain Pt, Pd, or Ni, and the second metallic layer may contain Ti or Al.
Regarding the above field effect transistor semiconductor, the metallic film of the gate electrode on the insulating film containing an SiO
2
film and defining an end of the gate electrode can be prevented from being stripped. Thus, an increase in the gate resistance can be prevented, resulting in high production yield.
The field effect transistor semiconductor in the present invention comprises a source/drain electrode positioned in a predetermined position in a semiconductor substrate, a channel region provided in the semiconductor substrate and between the source/drain electrodes, a gate electrode which is in schottky contact with a part of the channel region and is positioned between the source/drain electrodes, an insulating film which electrically insulates a surface of the semiconductor substrate and the gate electrode at both side surfaces of the gate electrode. And the gate electrode covers a part of the insulating film and the surface of the substrate serving as the channel region, and a thin film which is highly adhesive to the gate electrode is positioned between the insulating film and the gate electrode.
The thin film is a metallic film of tungsten (W), titan (Ti), molybdenum (Mo), or tungsten nitride (WN), or an alloy containing them.
Regarding the above structure, a thin film which is highly adhesive is inserted between the gate electrode containing Pt, Pd etc. and the insulating film. Thus the gate electrode can be prevented from being stripped.
The thin film can be silicon (Si) or an insulating film containing a large amount of silicon.
When Si or an insulating film containing a large amount of Si is inserted between the gate electrode and the insulating film, Pt, Pd etc. at the bottom layer of the gate electrode and Si react chemically to generate silicide by heat treatment. As a result, the adhesiveness improves further.
A method for manufacturing the field effect transistor in the present invention comprises a process for forming a first insulating film on a semiconductor substrate on which an operating layer is formed, a process for forming a photoresist pattern on the first insulating film, a process for forming a high density active layer by making the photoresist pattern as a mask, a process for forming a second insulating film on the first insulating film by making the photoresist pattern as a mask, a process for removing the photoresist and the second insulating film adhering thereon by a lift-off method, a process for forming a source/drain electrode in a region including at least a part of the high density active layer, a process for forming a photoresist pattern of overhang shape by photoresist coating, light exposure, and development, together with exposing a surface of the semiconductor substrate by removing the first insulating film by etching where the photoresist serves as a mask, further forming a bottom metallic layer being in schottky contact with the semiconductor by a vapor deposition m
Fujii Emi
Matsushita Shigeharu
Murai Shigeyuki
Tominaga Hisaaki
Arent Fox Kintner Plotkin & Kahn
Meier Stephen D.
Sanyo Electric Co,. Ltd.
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