Field effect transistor memory cell

Details Field effect transistor memory cell Field effect transistor memory cell

1971-08-24

1976-07-13

Fears, Terrell W.

Communications: electrical

Digital comparator systems

307238, 307279, 340173FF, G11C 1300, G11C 1140

Patent

active

RE0289051

ABSTRACT:
A cross-coupled flip-flop stage, or memory cell, for a word oriented array of memory cells is developed from four insulated-gate field-effect transistors which perform storage, loading, and gating functions of the cell. The functions of the cell are controlled by three different voltage levels coupled by a word line to all cells of a memory word.
Associated with the array are bipolar transistor wordline-select and digit-write circuits used for achieving a low select-read-write cycle time for the memory cells.

REFERENCES:
patent: 3390382 (1968-06-01), Igarashi
patent: 3447137 (1969-05-01), Feuer
patent: 3518635 (1970-06-01), Cole et al.
patent: 3541531 (1970-11-01), Iwersen
patent: 3870901 (1975-03-01), Smith et al.
patent: 3879621 (1975-04-01), Cavaliere et al.

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