Field effect transistor lost film fabrication process

Details Field effect transistor lost film fabrication process Field effect transistor lost film fabrication process

1976-03-29

1978-06-13

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

148 15, 148175, 357 54, 29579, H01L 2126

Patent

active

040940578

ABSTRACT:
This describes a process for fabricating transistor memory cell arrays which includes forming a thin oxide which is continuous over the entire area and which is continuously protected from the time it is deposited so that subsequent processing steps will not cause any change in the thickness of the thin oxide except where deliberately desired. By first depositing a protective masking film and subsequently removing this film in a series of steps, so that this film is lost in the fabrication process, the need for using the dual dielectric insulating layers required in the prior art can be eliminated. By eliminating such dual dielectric insulating layers the performance and density of the arrays can be improved.
Semiconductor arrays are formed by providing at a surface of a semiconductor substrate a pair of isolation lines and a plurality of conductive lines orthogonal to the isolation lines. Signal or bias voltages are applied to selected or predetermined conductive lines to provide control electrodes or field shields for the transistors. When the substrate has deposited on its surface an insulating medium, the dopant may be ion implanted through the insulating medium to form, e.g., the source and drain electrode of the transistors. Other elements may be added to the structure to form, e.g., a memory cell.

REFERENCES:
patent: 3351825 (1967-11-01), Vidas et al.
patent: 3791024 (1974-02-01), Boleky et al.
patent: 3894891 (1975-07-01), Magdo et al.
patent: 3919060 (1975-11-01), Pogge et al.

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