Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock
Patent
1990-08-13
1991-02-26
Miller, Stanley D.
Electrical transmission or interconnection systems
Personnel safety or limit control features
Interlock
307448, 307450, 307263, 307264, H03K 3353, H03K 19017
Patent
active
049964470
ABSTRACT:
A FET load circuit consists of two depletion-mode FETs connected in series. The gate of one FET is connected to ground. The gate of the other FET is connected to its source. This load circuit reduces power dissipation and provides superior operational stability, particularly in gallium-arsenide DCFL logic and memory circuits.
REFERENCES:
patent: 4195356 (1980-03-01), O'Connell et al.
patent: 4516225 (1985-05-01), Frederick
patent: 4521698 (1985-06-01), Taylor
patent: 4656372 (1987-04-01), Sani et al.
Copy of Certified Copy of U.S. application Ser. No. 641,797, filed Dec. 18, 1975 by Cranford et al.
Kagobutsu Handotai Debaisu II (Compound Semiconductor Devices II) first edition; by Imai, Ikoma, Sata, and Fujimoto, published Kogyo Chosakai on Jan. 10, 1985, pp. 6 to 9, and illustrated in FIG. 1.
IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct, 1987; pp. 699-703; A GaAs 16K SRAM with a Single 1-V Supply; Satoshi Takano, et al.
1986 IEEE GaAs IC Symposium; pp. 93-96; "A High-Speed GaAs 256x4-Bit Ram"; Grung et al.
1985 IEEE GaAs ICC Symposium; pp. 207-210; "A Fully Operational 1Kb Hemt Static Ram"; Kobayashi et al.
IBM Technical Disclosure Bulletin, vol. 29, No. 7, Dec. 1986; Digital Driver with Mesfets Having Three Difference Threshold Voltages; pp. 2885-2886.
Solid-State Electronics, vol. 30, No. 4, 1987; GaAs Inverted Common Drain Logic (ICDL) and Its Performance Compared with Other GaAs Logic Families; Ibrahim M. Abdel-Motaleb et al.; pp. 403-405.
Miller Stanley D.
OKI Electric Industry Co., Ltd.
Wambach M. R.
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