Field effect transistor inverter-level shifter circuitry

Details Field effect transistor inverter-level shifter circuitry Field effect transistor inverter-level shifter circuitry

1983-02-17

1986-02-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307584, H03K 19003, H03K 19094, H03K 1710

Patent

active

045688443

ABSTRACT:
A field effect transistor inverter-level shifter circuit which accepts TTL input level signals and generates MOS output level signals consists of the series combination of a load device, an enhancement mode transistor, and a depletion mode transistor. The gates of the enhancement and depletion mode transistors are connected to an input terminal. The source of the enhancement transistor is connected to the drain of the depletion transistor. The depletion transistor acts to control the potential of the source of the enhancement transistor so as to allow it to tolerate worse case TTL input potential "0" levels while not becoming more than only weakly biased on.

REFERENCES:
patent: 3675144 (1969-09-01), Zuk
patent: 3739194 (1973-06-01), Freeman et al.
patent: 4096584 (1978-06-01), Owen et al.
patent: 4109163 (1978-08-01), Cricchi et al.
patent: 4161663 (1979-07-01), Martinez
patent: 4346310 (1982-08-01), Carter
patent: 4396845 (1983-08-01), Nakano
patent: 4437025 (1984-03-01), Liu et al.
patent: 4438352 (1984-03-01), Mardkha
patent: 4469960 (1984-09-01), Raghunathan
patent: 4475050 (1984-10-01), Noufer
Fink et al., Electronics Engineers' Handbook, pp. 16-15 to 16-19, 1982.

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