Field effect transistor including a cap with a doped layer forme

Details Field effect transistor including a cap with a doped layer forme Field effect transistor including a cap with a doped layer forme

1993-11-10

1996-07-02

Brown, Peter Toby

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

257280, 257287, H01L 29812

Patent

active

055325050

ABSTRACT:
This invention aims at providing an high output FET having a planar type-gate structure suitable for integration, and a structure that suppresses long gate effect. A heavily doped thin channel layer 13 is formed on a semiconductor substrate 11, and a cap layer including a doped layer 15 is formed on the channel layer 13. A thickness and a dopant concentration of the doped layer 15 are so set that the doped layer 15 per se is depleted by a surface depletion region resulting from an interface level of the semiconductor substrate surface, and the surface depletion region does not widen to the channel layer 13. Consequently no long gate effect takes place on the side where a gate bias is lower.

REFERENCES:
patent: 4163984 (1979-08-01), Purcel
patent: 4673959 (1987-06-01), Shiraki et al.
patent: 4814838 (1989-03-01), Kuroda et al.
patent: 4882609 (1989-11-01), Schubert et al.
patent: 5151758 (1992-09-01), Smith
H. Sakaki, Velocity-Modulation Transistor-A New Field Effect Transistor Concept, Japanese Journal of Applied Physics, vol. 1, No. 6, Jun. 1982, pp. L381-L383.
"GaAs MESFET's Fabricated By New Self-Alignment Technology," Extended Abstracts of the 19th Conference on Solid State Devices and Materials, Tokyo, 1987, by Eiji Yanokura et al. pp. 263-266.
"Long Gate Effect Due To Gate-Drain Surface Depletion Layer In GaAs MESFETs," by Hiroshi Mizuta et al., 1986, 8 pages.
Patent Abstracts of Japan vol. 010091 (E-394) 9 Apr. 1986, Tatsuya et al., Man. of Semiconductor Device.

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