Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – On insulating substrate or layer
Reexamination Certificate
2001-06-01
2002-07-02
Ho, Hoai V. (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
On insulating substrate or layer
C438S226000, C438S231000, C438S232000, C257S066000, C257S347000, C257S349000
Reexamination Certificate
active
06413829
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor in SOI (semiconductor on insulator) technology with schottky-contact extensions, for minimizing short-channel effects in the field effect transistor and for reducing the threshold voltage of the field effect transistor.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension junction
104
and a source extension junction
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension junction
104
and the source extension junction
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where a MOSFET is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
As the dimensions of the MOSFET
100
are scaled down further, the junction capacitances formed by the drain and source extension junctions
104
and
106
and by the drain and source contact junctions
108
and
112
may limit the speed performance of the MOSFET
100
. Thus, referring to
FIG. 2
, a MOSFET
150
is formed with SOI (semiconductor on insulator) technology. In that case, a layer of buried insulating material
152
is formed on the semiconductor substrate
102
, and a layer of semiconductor material
154
is formed on the layer of buried insulating material
152
. A drain
156
and a source
158
of the MOSFET
150
are formed in the layer of semiconductor material
154
. Elements such as the gate dielectric
116
and the gate electrode
118
having the same reference number in
FIGS. 1 and 2
refer to elements having similar structure and function. Processes for formation of such elements
116
,
118
,
152
,
154
,
156
, and
158
of the MOSFET
150
are known to one of ordinary skill in the art of integrated circuit fabrication.
In
FIG. 2
, the drain
156
and the source
158
are formed to extend down to contact the layer of buried insulating material
152
. Thus, because the drain
156
, the source
158
, and a channel region
160
of the MOSFET
150
do not form a junction with the semiconductor substrate
102
, junction capacitance is minimized for the MOSFET
150
to enhance the speed performance of the MOSFET
150
formed with SOI (semiconductor on insulator) technology.
In addition, referring to
FIG. 2
, as the dimensions of the MOSFET
150
are scaled down further, the occurrence of undesired short-channel effects increases, as known to one of ordinary skill in the art of integrated circuit fabrication. With short-channel effects, the threshold voltage of the MOSFET
150
changes such that electrical characteristics of such a MOSFET become uncontrollable, as known to one of ordinary skill in the art of integrated circuit fabrication. In the MOSFET
150
of
FIG. 2
, the layer of semiconductor material
154
is formed to be thin to minimize undesired short-channel effects. However, a low volume of silicide formed with such a thin layer of semiconductor material
154
results in high series resistance at the drain and the source of the MOSFET
150
. Furthermore, as dimensions of the MOSFET
150
are scaled down, a lower threshold voltage is desired for scaling down the bias voltages during operation of the MOSFET
150
.
Thus, a mechanism is desired for forming a MOSFET with minimized short channel effects and with lower threshold voltage but with higher volume of drain and source contact silicide for the MOSFET formed in SOI (semiconductor on insulator) technology.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a field effect transistor is fabricated with schottky drain and source extension silicides to minimize short channel effects and for lower threshold voltage. In addition, drain and source contact silicides are formed to have maximized volume to minimize series resistance at the drain and source of the field effect transistor formed in SOI (semiconductor on insulator) technology.
In one embodiment of the present invention, for fabricating a field effect transistor on a buried insulating material in SOI (semiconductor on insulator) technology, a gate dielectric and a gate electrode are formed on the semiconductor material, and spacers are formed on sidewalls of the gate electrode and the gate dielectric. The spacers cover portions of the semiconductor material. A dopant is implanted into exposed regions of the semiconductor material to form a drain doped region and a source doped region. A portion of the drain doped region and a portion of the source doped region extend under the spacers. A drain contact silicide is formed with an exposed portion of the drain doped region, and a source contact silicide is formed with an exposed portion of the source doped region. The spacers are removed to expose the portions of the semiconductor material including a portion of the drain doped region and a portion of the source doped region. A drain extension silicide is formed with a first exposed portion of the semiconductor material disposed between the drain contact silicide and the gate dielectric, and the drain extension silicide is formed also on the portion of the drain doped region disposed by the drain contact silicide. A source extension silicide is formed with a second exposed portion of the semiconductor material disposed between the source contact silicide and the gate dielectric, and the source extension silicide is formed also on the portion of the source doped region disposed by the source contact silicide.
The present invention may be used to particular advantage when additional semiconductor material is epitaxially grown on the exposed portion of the drain doped region to form an elevated drain structure and on the exposed p
Advanced Micro Devices , Inc.
Choi Monica H.
Ho Hoai V.
Tran Mai-Huong
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