Field effect transistor having substantially coplanar surface st

Details Field effect transistor having substantially coplanar surface st Field effect transistor having substantially coplanar surface st

1990-10-31

1992-03-10

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 60, 437192, 437203, 437 59, H01L 21283, H01L 21334

Patent

active

050949659

ABSTRACT:
A semiconductor device has MOS field effect transistors isolated by a field shield. The field shield has a gate of conductor layers formed spaced apart from each other on a silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. In regions isolated by the field shield, MOS field effect transistors are formed. Each of the MOS field effect transistors has a gate electrode of a conductor layer formed on the silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. An impurity diffused region is formed in a region on the silicon substrate between the gate electrode and the field shield. A portion on an exposed surface of the impurity diffused region between the field shield and the gate electrode is selectively filled with a tungsten buried layer. The tungsten buried layer is formed, flattened relative to the gate electrode and the gate constituting the field shield.

REFERENCES:
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patent: 4868138 (1989-09-01), Chan et al.
patent: 4992389 (1991-02-01), Ogura et al.
Nishiyama et al., "Two Step Tungsten Selective CVD for High Speed CMOS Device Applications", IEEE VLSI Symposium, pp. 97-98.

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