Field effect transistor having control and current electrodes po

Details Field effect transistor having control and current electrodes po Field effect transistor having control and current electrodes po

1991-09-30

1992-10-27

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 29, 437 35, 437 41, 437 59, 437 89, 437913, 148DIG53, H01L 21265

Patent

active

051589010

ABSTRACT:
A field effect transistor having regions (20, 20', and 20") which respectively function as a planar elevated surface for gate, drain, and source electrical contact, and method of fabrication. The transistor overlies a substrate (12) and is formed partially from active areas (14 and 14'). The regions (20, 20', and 20"), each underlie or are surrounded by a dielectric layer (22). A gate is formed by a gate layer (24). A source (30) is formed within region (20") and is electrically connected to active area (14'). A drain (30') and channel region are formed within region (20'). Electrical contact is made to the source (30), drain (30') and gate layer (24) by conductive layers (34", 34', and 34, respectively).

REFERENCES:
patent: 3938241 (1976-02-01), George et al.
patent: 4849369 (1989-07-01), Jeuch et al.
patent: 5001078 (1991-03-01), Wada
patent: 5079180 (1992-01-01), Rodder et al.
"Impact of Surrounding Gate Transistor (SGT) for Ultra-High-Density LSI's," by H. Takato et al., IEEE Transactions on Electronic Devices, vol. 38, Mar. 1991, pp. 573-577.

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