Field effect transistor having an extremely short channel length

Metal working – Method of mechanical manufacture – Assembling or joining

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29591, 148 15, 148187, 357 23, H01L 2126

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043063527

ABSTRACT:
A field effect transistor having an extremely short channel length in which a doped semiconductor layer of one conductivity type has oppositely doped source and drain zones in a surface side thereof. A first gate electrode is separated from the semiconductor layer surface by an insulating layer. The first gate electrode covers the region between the source and drain zones with the exception of a strip-like semiconductor region directly adjoining the source zone. A second gate electrode is provided above the strip-like semiconductor region and is insulated from the first gate electrode by a second insulating layer. The first gate electrode is connected to a bias voltage source and the second gate electrode is arranged to be connected to a control voltage.

REFERENCES:
patent: 3454844 (1969-07-01), Dill
patent: 3660697 (1972-05-01), Berglund et al.
patent: 3912545 (1975-10-01), Armstrong
patent: 3996658 (1976-12-01), Takei et al.
patent: 4031608 (1977-06-01), Togei et al.
patent: 4037308 (1977-07-01), Smith
patent: 4084108 (1978-04-01), Fujimoto
patent: 4091278 (1978-05-01), Tchon
IEEE Journal of Solid-State Circuits, vol. SC-10, No. 5, Oct. 1975, pp. 322-331.

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