Field effect transistor having a sandwiched channel layer

Details Field effect transistor having a sandwiched channel layer Field effect transistor having a sandwiched channel layer

1992-04-21

1994-07-19

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

257191, 257190, 257194, 257 12, H01L 29360, H01L 29680

Patent

active

053314107

ABSTRACT:
An FET includes an epitaxially grown n-type GaInAs channel layer, first and second undoped GaInAs layers formed to sandwich the channel layer, a buffer layer formed on a GaAs substrate to be in contact with one side of the first layer, and an undoped cap layer formed to be in contact with one side of the second layer. Each of the first and second undoped GaInAs layers is a graded layer in which the In composition ratio is gradually varied such that the In composition ratio is high on the channel layer side and is low on the buffer layer side and the cap layer side. A region in which carrier electrons are present is not entirely located on the channel layer, but a part of the region extends to the undoped GaInAs layers. For this reason, carrier electrons present in the undoped GaInAs layers are not scattered by dopant atoms, and the carrier electrons are permitted to move at high speed, thereby decreasing the source resistance and increasing the transconductance (g.sub.m). High-speed operation with low noise can be achieved.

REFERENCES:
patent: 4163237 (1979-07-01), Dingle et al.
patent: 4691215 (1987-09-01), Luryi et al.
patent: 5060030 (1991-10-01), Hoke
patent: 5091759 (1992-02-01), Shih et al.
patent: 5206527 (1993-04-01), Kuwata

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