Patent
1991-04-16
1992-10-20
Mintel, William
357239, 357 54, 357 71, H01L 2968, H01L 2906, H01L 2934, H01L 2348
Patent
active
051574691
ABSTRACT:
A field effect transistor and a method of manufacturing thereof are disclosed that is not reduced in the characteristic of withstanding voltage between multilayer interconnection layers even when scaled to a higher integration. This field effect transistor includes side walls 21a formed on both sides of a bit line 15 so that the bottom side end contacts the upper surface of side walls 20a of gate electrodes 4b and 4c. The thickness of an insulating film interposed between gate electrodes 4b and 4c and a base portion 11a forming a low electrode 11 of a capacitor is not reduced. The characteristic of withstanding voltage is not deteriorated between multilayer interconnection layers even when scaled to higher integration.
REFERENCES:
patent: 4970564 (1990-11-01), Kimura et al.
Watanabe et al., "Stacked Capacitor Cells for High-Density Dynmic RAMs," IEEE 1988, pp. 600-603.
Kimura et al., "An Optically Delineated 4.2 .mu.m.sup.2 Self-Aligned Isolated-Plate Stacked-Capacitor DRAM Cell," IEEE Transactions on Electron Devices, vol. 35, No. 10 (Oct. 1988), pp. 1591-1594.
Koyanagi et al., "Novel High Density, Stacked Capacitor MOS RAM," IEEE (1978), pp. 348-351.
Arima Hideaki
Matsui Yasushi
Motonami Kaoru
Ohi Makoto
Okudaira Tomonori
Limanek Robert
Mintel William
Mitsubishi Denki & Kabushiki Kaisha
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