Field effect transistor having a low threshold voltage shift

Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With specified crystal plane or axis

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257420, 257255, H01L 2904

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054422272

ABSTRACT:
The main surface of a semiconductor substrate, on which a field effect transistor is formed, coincides with the (nm0) lattice plane of the substrate and drain electrode thereof is oriented to flow drain current in a direction parallel to the [mn0] or [mn0] axis, wherein n and m independently represent an arbitrary integer, provided that n and m are not 0 at the same time, and that the quotient n/m (m is not zero) is not an integer. Accordingly, the plane orientation of the substrate and the direction of the drain current have a relationship such that no piezoelectric charges are induced in the channel region of the field effect transistor. Therefore, substantially no piezoelectric charges are generated even when a stress is produced in the dielectric layer formed on the substrate. Moreover, deterioration and variation in the electric characteristics due to the variation in the thickness of the dielectric layer are minimized.

REFERENCES:
patent: 4423434 (1983-12-01), Komatsu
patent: 4758896 (1988-07-01), Ito
patent: 4791471 (1988-12-01), Onodera et al.
patent: 4980750 (1990-12-01), Ueno
"Piezoelectric Effects in GaAs FET's and Their Role in Orientation-Dependent Device Characteristics", IEEE Transactions on Electron Devices, vol. ED-31, No. 10, Oct. 1984 by Peter M. Asbeck et al. pp. 1377-1380.
"Theoretical Study of the Piezoelectric Effect on GaAs MESFET's on (100), (011), and (111)Ga, and (111) As Substrates", IEEE Transactions on Electron Devices, vol. 36, No. 9, Sep. 1989, T. Onodera et al. pp. 1580-1585.
"Experimental Study of the Orientation Effect of GaAs MESFET's Fabricated on (100), (011), and (111)Ga, and (111) As Substrates", IEEE Transactions on Electron Devices, vol. 36, No. 9, Sep. 1989, T. Onodera et al. pp. 1586-1590.

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